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Hdlmake
Commits
6d763a1d
Commit
6d763a1d
authored
Mar 13, 2017
by
Javier D. Garcia-Lasheras
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Plain Diff
Fix minor style issues
parent
918438b5
Hide whitespace changes
Inline
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Showing
4 changed files
with
19 additions
and
14 deletions
+19
-14
git.py
hdlmake/fetch/git.py
+7
-7
content.py
hdlmake/module/content.py
+4
-2
diamond.py
hdlmake/tools/diamond.py
+1
-1
quartus.py
hdlmake/tools/quartus.py
+7
-4
No files found.
hdlmake/fetch/git.py
View file @
6d763a1d
...
...
@@ -49,9 +49,9 @@ class Git(Fetcher):
shell
=
True
)
tree_root_line
=
tree_root_cmd
.
stdout
.
readlines
()[
0
]
.
strip
()
return
tree_root_line
except
CalledProcessError
as
e
:
print
e
.
output
logging
.
error
(
"Cannot get the top level!"
)
except
CalledProcessError
as
process_error
:
logging
.
error
(
"Cannot get the top level!:
%
s"
,
process_error
.
output
)
quit
()
@
staticmethod
...
...
@@ -74,9 +74,9 @@ class Git(Fetcher):
return
None
else
:
return
None
except
CalledProcessError
as
e
:
print
e
.
output
logging
.
error
(
"Cannot get the submodule status!"
)
except
CalledProcessError
as
process_error
:
logging
.
error
(
"Cannot get the submodule status!:
%
s"
,
process_error
.
output
)
quit
()
def
fetch
(
self
,
module
):
...
...
@@ -99,7 +99,7 @@ class Git(Fetcher):
else
:
logging
.
info
(
"Updating git module
%
s"
,
mod_path
)
checkout_id
=
None
if
module
.
branch
is
not
None
:
if
module
.
branch
is
not
None
:
checkout_id
=
module
.
branch
logging
.
debug
(
"Git branch requested:
%
s"
,
checkout_id
)
elif
module
.
revision
is
not
None
:
...
...
hdlmake/module/content.py
View file @
6d763a1d
...
...
@@ -110,8 +110,10 @@ class ModuleContent(ModuleCore):
# Included Makefiles
included_makefiles_aux
=
[]
if
"incl_makefiles"
in
self
.
manifest_dict
:
if
isinstance
(
self
.
manifest_dict
[
"incl_makefiles"
],
six
.
string_types
):
included_makefiles_aux
.
append
(
self
.
manifest_dict
[
"incl_makefiles"
])
if
isinstance
(
self
.
manifest_dict
[
"incl_makefiles"
],
six
.
string_types
):
included_makefiles_aux
.
append
(
self
.
manifest_dict
[
"incl_makefiles"
])
else
:
# list
included_makefiles_aux
=
self
.
manifest_dict
[
"incl_makefiles"
][:]
makefiles_paths
=
self
.
_make_list_of_paths
(
included_makefiles_aux
)
...
...
hdlmake/tools/diamond.py
View file @
6d763a1d
...
...
@@ -46,7 +46,7 @@ class ToolDiamond(ToolSyn):
SUPPORTED_FILES
=
{
EDFFile
:
_LATTICE_SOURCE
.
format
(
'add'
),
LPFFile
:
_LATTICE_SOURCE
.
format
(
'add -exclude'
)
+
'
\n
'
+
LPFFile
:
_LATTICE_SOURCE
.
format
(
'add -exclude'
)
+
'
\n
'
+
_LATTICE_SOURCE
.
format
(
'enable'
)}
HDL_FILES
=
{
...
...
hdlmake/tools/quartus.py
View file @
6d763a1d
...
...
@@ -53,7 +53,7 @@ class ToolQuartus(ToolSyn):
SUPPORTED_FILES
=
{
SignalTapFile
:
_QUARTUS_SOURCE
.
format
(
'SIGNALTAP_FILE'
),
SDCFile
:
_QUARTUS_SOURCE
.
format
(
'SDC_FILE'
),
QIPFile
:
_QUARTUS_SOURCE
.
format
(
'QIP_FILE'
),
QIPFile
:
_QUARTUS_SOURCE
.
format
(
'QIP_FILE'
),
QSYSFile
:
_QUARTUS_SOURCE
.
format
(
'QSYS_FILE'
),
DPFFile
:
_QUARTUS_SOURCE
.
format
(
'MISC_FILE'
),
QSFFile
:
_QUARTUS_SOURCE
.
format
(
'SOURCE_TCL_SCRIPT_FILE'
),
...
...
@@ -66,9 +66,12 @@ class ToolQuartus(ToolSyn):
_QUARTUS_LIBRARY
=
" -library {0}"
.
format
(
'work'
)
HDL_FILES
=
{
VHDLFile
:
_QUARTUS_SOURCE
.
format
(
'VHDL_FILE'
)
+
_QUARTUS_LIBRARY
,
VerilogFile
:
_QUARTUS_SOURCE
.
format
(
'SYSTEMVERILOG_FILE'
)
+
_QUARTUS_LIBRARY
,
SVFile
:
_QUARTUS_SOURCE
.
format
(
'VERILOG_FILE'
)
+
_QUARTUS_LIBRARY
}
VHDLFile
:
_QUARTUS_SOURCE
.
format
(
'VHDL_FILE'
)
+
_QUARTUS_LIBRARY
,
VerilogFile
:
_QUARTUS_SOURCE
.
format
(
'SYSTEMVERILOG_FILE'
)
+
_QUARTUS_LIBRARY
,
SVFile
:
_QUARTUS_SOURCE
.
format
(
'VERILOG_FILE'
)
+
_QUARTUS_LIBRARY
}
CLEAN_TARGETS
=
{
'clean'
:
[
"*.rpt"
,
"*.smsg"
,
"run.tcl"
,
"*.summary"
,
"*.done"
,
"*.jdi"
,
"*.pin"
,
"*.qws"
,
...
...
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