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Hdlmake
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71b60dde
Commit
71b60dde
authored
Apr 03, 2019
by
Javier D. Garcia-Lasheras
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Do not try to synthesize Verilog and SystemVerilog includes
parent
a348e326
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-1
make_syn.py
hdlmake/tools/make_syn.py
+6
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hdlmake/tools/make_syn.py
View file @
71b60dde
...
@@ -116,7 +116,12 @@ endif""")
...
@@ -116,7 +116,12 @@ endif""")
file_list
=
[]
file_list
=
[]
for
file_aux
in
self
.
fileset
:
for
file_aux
in
self
.
fileset
:
if
isinstance
(
file_aux
,
filetype
):
if
isinstance
(
file_aux
,
filetype
):
if
not
(
filetype
==
VerilogFile
and
isinstance
(
file_aux
,
SVFile
)):
if
(
not
(
filetype
==
VerilogFile
and
isinstance
(
file_aux
,
SVFile
))
and
not
(
isinstance
(
file_aux
,
VerilogFile
)
and
file_aux
.
is_include
)
):
file_list
.
append
(
shell
.
tclpath
(
file_aux
.
rel_path
()))
file_list
.
append
(
shell
.
tclpath
(
file_aux
.
rel_path
()))
if
not
file_list
==
[]:
if
not
file_list
==
[]:
ret
.
append
(
ret
.
append
(
...
...
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