Remove blank line from Xilinx TCL error checking

754e247d · Javier D. Garcia-Lasheras · 91c3b301 · 754e247d
Commit 754e247d authored Mar 06, 2017 by Javier D. Garcia-Lasheras
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xilinx.py hdlmake/tools/xilinx.py +1 -1

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--- a/hdlmake/tools/xilinx.py
+++ b/hdlmake/tools/xilinx.py
@@ -38,7 +38,7 @@ class ToolXilinx(ToolSyn):

    CLEAN_TARGETS = {'mrproper': ["*.bit", "*.bin"]}

-    _XILINX_RUN = '''
+    _XILINX_RUN = '''\
 reset_run {0}
 launch_runs {0}
 wait_on_run {0}