| ``file`` | this is a file (included by the module that has been previously printed) |
| ``file`` | this is a file (included by the module that has been previously printed) |
...
@@ -1314,22 +1312,26 @@ Currently, the following FPGA IDEs are supported:
...
@@ -1314,22 +1312,26 @@ Currently, the following FPGA IDEs are supported:
.. note:: both ``ise-project`` and ``quartus-project`` commands has been mantained in the code for backwards compatiblity. In any case, when any of these are found, the general ``project`` action is launched.
.. note:: both ``ise-project`` and ``quartus-project`` commands has been mantained in the code for backwards compatiblity. In any case, when any of these are found, the general ``project`` action is launched.
Automatic execution (``auto``)
Makefile generation (``makefile``)
------------------------------
----------------------------------
This is the default action for hdlmake, the one that is run when a command is not given.
This is the default command for ``hdlmake`` and its basic behaviour will be defined by the value of the ``action`` manifest parameter in the hierachy ``Manifest.py``. ``action`` can be set to ``simulation`` or ``synthesis``, and the associated command sequence will be:
.. note:: The ``auto`` command is just inferred if the issued command is a plain ``hdlmake``. If an optional argument is provided, you need to specify the specific command that is going to be executed.
- **simulation**: generate a simulation makefile including all the files required for the defined testbench
- **synthesis**: generate a synthesis makefile including all the files required for bitstream generation
The basic behaviour will be defined by the value of the ``action`` manifest parameter in the hierachy top ``Manifest.py``. This can be set to ``simulation`` or ``synthesis``, and the associated command sequence will be:
By using the ``-f FILENAME``, ``--filename FILENAME`` optional argument for the ``makefile`` command, we can choose the name of the synthesis or simulation Makefile that will be generated by ``hdlmake``.
**simulation**:
In order to allow for a more agile development, we have included these shortcuts when using the ``hdlmake makefile`` command:
#. generate a simulation makefile including all the files required for the defined testbench
.. code-block:: bash
**synthesis**:
# These commands are equivalent
hdlmake makefile
hdlmake
#. create/update the FPGA project including all the files required for bitstream generation
# These commands are equivalent
#. generate a synthesis makefile
hdlmake makefile -f FILENAME
hdlmake -f FILENAME
.. note:: in any case, it's supposed that all the required modules have been previously fetched. Otherwise, the process will fail.
.. note:: in any case, it's supposed that all the required modules have been previously fetched. Otherwise, the process will fail.
