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Hdlmake
Commit 844c0f10 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Run Autopep8 aggressive for tools files

parent f782f1dc
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Showing with 607 additions and 418 deletions
hdlmake/tools/__init__.py
View file @ 844c0f10
......@@ -12,4 +12,3 @@ from .vivado import ToolVivado
from .quartus import ToolQuartus
from .diamond import ToolDiamond
from .libero import ToolLibero
hdlmake/tools/active_hdl.py
View file @ 844c0f10
......@@ -33,7 +33,7 @@ class ToolActiveHDL(MakefileWriter):
def detect_version(self, path):
pass
def get_keys(self):
tool_info = {
'name': 'Aldec Active-HDL',
......@@ -53,7 +53,6 @@ class ToolActiveHDL(MakefileWriter):
# Return an empty fileset
return sup_files
def generate_simulation_makefile(self, fileset, top_module):
# TODO: ??
from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile
......@@ -72,24 +71,39 @@ simulation:
)
self.write(makefile_text_1)
self.writeln("\t\techo \"# Active-HDL command file, generated by HDLMake\" > run.command")
self.writeln(
"\t\techo \"# Active-HDL command file, generated by HDLMake\" > run.command")
self.writeln()
self.writeln("\t\techo \"# Create library and set as default target\" >> run.command")
self.writeln(
"\t\techo \"# Create library and set as default target\" >> run.command")
self.writeln("\t\techo \"alib work\" >> run.command")
self.writeln("\t\techo \"set worklib work\" >> run.command")
self.writeln()
self.writeln("\t\techo \"# Compiling HDL source files\" >> run.command")
self.writeln(
"\t\techo \"# Compiling HDL source files\" >> run.command")
for vl in fileset.filter(VerilogFile):
self.writeln("\t\techo \"alog " + vl.rel_path() + "\" >> run.command")
self.writeln(
"\t\techo \"alog " +
vl.rel_path(
) +
"\" >> run.command")
for sv in fileset.filter(SVFile):
self.writeln("\t\techo \"alog " + sv.rel_path() + "\" >> run.command")
self.writeln(
"\t\techo \"alog " +
sv.rel_path(
) +
"\" >> run.command")
for vhdl in fileset.filter(VHDLFile):
self.writeln("\t\techo \"acom " + vhdl.rel_path() + "\" >> run.command")
self.writeln(
"\t\techo \"acom " +
vhdl.rel_path(
) +
"\" >> run.command")
self.writeln()
makefile_tmplt_2 = string.Template("""
makefile_tmplt_2 = string.Template("""
\t\tvsimsa -do run.command
sim_pre_cmd:
......@@ -120,10 +134,8 @@ mrproper: clean
else:
sim_post_cmd = ''
makefile_text_2 = makefile_tmplt_2.substitute(
sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd,
)
self.write(makefile_text_2)
hdlmake/tools/diamond.py
View file @ 844c0f10
......@@ -98,28 +98,29 @@ mrproper:
else:
syn_post_cmd = ''
if sys.platform == 'cygwin':
bin_name = 'pnmainc'
bin_name = 'pnmainc'
else:
bin_name = 'diamondc'
makefile_text = makefile_tmplt.substitute(syn_top=top_mod.manifest_dict["syn_top"],
project_name=top_mod.manifest_dict["syn_project"],
diamond_path=tool_path,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
diamondc_path=os.path.join(tool_path, bin_name))
bin_name = 'diamondc'
makefile_text = makefile_tmplt.substitute(
syn_top=top_mod.manifest_dict["syn_top"],
project_name=top_mod.manifest_dict[
"syn_project"],
diamond_path=tool_path,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
diamondc_path=os.path.join(tool_path, bin_name))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
def generate_remote_synthesis_makefile(self, files, name, cwd, user, server):
def generate_remote_synthesis_makefile(
self, files, name, cwd, user, server):
logging.info("Remote Diamond wrapper")
def generate_synthesis_project(self, update=False, tool_version='', top_mod=None, fileset=None):
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
self.files = []
self.filename = top_mod.manifest_dict["syn_project"]
self.header = None
......@@ -128,57 +129,56 @@ mrproper:
self.update_project()
else:
self.create_project(top_mod.manifest_dict["syn_device"],
top_mod.manifest_dict["syn_grade"],
top_mod.manifest_dict["syn_package"],
top_mod.manifest_dict["syn_top"])
top_mod.manifest_dict["syn_grade"],
top_mod.manifest_dict["syn_package"],
top_mod.manifest_dict["syn_top"])
self.add_files(fileset)
self.emit(update=update)
self.execute()
self.execute()
def emit(self, update=False):
f = open(self.tclname, "w")
f.write(self.header+'\n')
f.write(self.header + '\n')
f.write(self.__emit_files(update=update))
f.write('prj_project save\n')
f.write('prj_project close\n')
f.close()
def execute(self):
# The binary name for Diamond is different in Linux and Windows
# The binary name for Diamond is different in Linux and Windows
if sys.platform == 'cygwin':
tmp = 'pnmainc {0}'
else:
tmp = 'diamondc {0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
## But do not wait till diamond finish, start displaying output immediately ##
# But do not wait till diamond finish, start displaying output
# immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() != None:
if out == '' and p.poll() is not None:
break
if out != '':
sys.stdout.write(out)
sys.stdout.flush()
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
def create_project(self,
def create_project(self,
syn_device,
syn_grade,
syn_package,
syn_top):
tmp = 'prj_project new -name {0} -impl {0} -dev {1} -synthesis \"synplify\"'
target = syn_device+syn_grade+syn_package
target = syn_device + syn_grade + syn_package
self.header = tmp.format(self.filename, target.upper())
def update_project(self):
tmp = 'prj_project open \"{0}\"'
self.header = tmp.format(self.filename+'.ldf')
self.header = tmp.format(self.filename + '.ldf')
def supported_files(self, fileset):
from hdlmake.srcfile import EDFFile, LPFFile, SourceFileSet
......@@ -190,7 +190,6 @@ mrproper:
continue
return sup_files
def __emit_files(self, update=False):
tmp = 'prj_src {0} \"{1}\"'
ret = []
......@@ -198,17 +197,17 @@ mrproper:
for f in self.files:
line = ''
if isinstance(f, VHDLFile) or isinstance(f, VerilogFile) or isinstance(f, SVFile) or isinstance(f, EDFFile):
if update == True:
line = line+'\n'+tmp.format('remove', f.rel_path())
line = line+'\n'+tmp.format('add', f.rel_path())
if update:
line = line + '\n' + tmp.format('remove', f.rel_path())
line = line + '\n' + tmp.format('add', f.rel_path())
elif isinstance(f, LPFFile):
if update == True:
line = line+'\n'+tmp.format('enable', self.filename+'.lpf')
line = line+'\n'+tmp.format('remove', f.rel_path())
line = line+'\n'+tmp.format('add -exclude', f.rel_path())
line = line+'\n'+tmp.format('enable', f.rel_path())
if update:
line = line + '\n' + \
tmp.format('enable', self.filename + '.lpf')
line = line + '\n' + tmp.format('remove', f.rel_path())
line = line + '\n' + tmp.format('add -exclude', f.rel_path())
line = line + '\n' + tmp.format('enable', f.rel_path())
else:
continue
ret.append(line)
return ('\n'.join(ret))+'\n'
return ('\n'.join(ret)) + '\n'
hdlmake/tools/ghdl.py
View file @ 844c0f10
......@@ -33,7 +33,6 @@ class ToolGHDL(MakefileWriter):
def detect_version(self, path):
pass
def get_keys(self):
tool_info = {
'name': 'GHDL',
......@@ -47,16 +46,14 @@ class ToolGHDL(MakefileWriter):
GHDL_STANDARD_LIBS = ['ieee', 'std']
return GHDL_STANDARD_LIBS
def supported_files(self, fileset):
from hdlmake.srcfile import SourceFileSet
sup_files = SourceFileSet()
return sup_files
def generate_simulation_makefile(self, fileset, top_module):
# TODO: vhdl87 vs vhdl97 options
from hdlmake.srcfile import VHDLFile
makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module}
......@@ -84,7 +81,7 @@ simulation:
self.writeln("\t\tghdl -e $(TOP_MODULE)")
self.writeln()
makefile_tmplt_2 = string.Template("""
makefile_tmplt_2 = string.Template("""
sim_pre_cmd:
\t\t${sim_pre_cmd}
......@@ -113,7 +110,6 @@ mrproper: clean
else:
sim_post_cmd = ''
makefile_text_2 = makefile_tmplt_2.substitute(
sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd,
......
hdlmake/tools/ise.py
View file @ 844c0f10
This diff is collapsed.
hdlmake/tools/isim.py
View file @ 844c0f10
This diff is collapsed.
hdlmake/tools/iverilog.py
View file @ 844c0f10
......@@ -31,10 +31,11 @@ from hdlmake.makefile_writer import MakefileWriter
IVERILOG_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'simprim', 'unisim', 'unimacro', 'aim', 'cpld',
'pls', 'xilinxcorelib', 'aim_ver', 'cpld_ver',
'simprims_ver', 'unisims_ver', 'uni9000_ver',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
'simprim', 'unisim', 'unimacro', 'aim', 'cpld',
'pls', 'xilinxcorelib', 'aim_ver', 'cpld_ver',
'simprims_ver', 'unisims_ver', 'uni9000_ver',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
class ToolIVerilog(MakefileWriter):
......@@ -54,8 +55,10 @@ class ToolIVerilog(MakefileWriter):
return IVERILOG_STANDARD_LIBS
def detect_version(self, path):
if platform.system() == 'Windows': is_windows = True
else: is_windows = False
if platform.system() == 'Windows':
is_windows = True
else:
is_windows = False
iverilog = Popen("iverilog -v 2>/dev/null| awk '{if(NR==1) print $4}'",
shell=True,
stdin=PIPE,
......@@ -64,15 +67,14 @@ class ToolIVerilog(MakefileWriter):
version = iverilog.stdout.readlines()[0].strip()
return version
def supported_files(self, fileset):
from hdlmake.srcfile import SourceFileSet
sup_files = SourceFileSet()
return sup_files
def generate_simulation_makefile(self, fileset, top_module):
# TODO FLAGS: 2009 enables SystemVerilog (ongoing support) and partial VHDL support
# TODO FLAGS: 2009 enables SystemVerilog (ongoing support) and partial
# VHDL support
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
......@@ -92,7 +94,8 @@ simulation:
)
self.write(makefile_text_1)
self.writeln("\t\techo \"# IVerilog command file, generated by HDLMake\" > run.command")
self.writeln(
"\t\techo \"# IVerilog command file, generated by HDLMake\" > run.command")
for inc in top_module.get_include_dirs_list():
self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command")
......@@ -106,7 +109,6 @@ simulation:
for sv in fileset.filter(SVFile):
self.writeln("\t\techo \"" + sv.rel_path() + "\" >> run.command")
makefile_tmplt_2 = string.Template("""
\t\tiverilog ${iverilog_opt} -s $$(TOP_MODULE) -o $$(TOP_MODULE).vvp -c run.command
......@@ -142,12 +144,9 @@ mrproper: clean
else:
sim_post_cmd = ''
makefile_text_2 = makefile_tmplt_2.substitute(
iverilog_opt=iverilog_opt,
sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd,
)
self.write(makefile_text_2)
hdlmake/tools/libero.py
View file @ 844c0f10
......@@ -41,7 +41,6 @@ class ToolLibero(MakefileWriter):
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'Libero',
......@@ -100,24 +99,25 @@ mrproper:
else:
syn_post_cmd = ''
makefile_text = makefile_tmplt.substitute(syn_top=top_mod.manifest_dict["syn_top"],
project_name=top_mod.manifest_dict["syn_project"],
libero_path=tool_path,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
libero_sh_path=os.path.join(tool_path, "libero"))
makefile_text = makefile_tmplt.substitute(
syn_top=top_mod.manifest_dict["syn_top"],
project_name=top_mod.manifest_dict[
"syn_project"],
libero_path=tool_path,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
libero_sh_path=os.path.join(tool_path, "libero"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
def generate_remote_synthesis_makefile(self, files, name, cwd, user, server):
def generate_remote_synthesis_makefile(
self, files, name, cwd, user, server):
logging.info("Remote Libero wrapper")
def generate_synthesis_project(self, update=False, tool_version='', top_mod=None, fileset=None):
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
self.files = []
self.filename = top_mod.manifest_dict["syn_project"]
self.syn_device = top_mod.manifest_dict["syn_device"]
......@@ -133,12 +133,11 @@ mrproper:
self.create_project()
self.add_files(fileset)
self.emit()
self.execute()
self.execute()
def emit(self, update=False):
f = open(self.tclname, "w")
f.write(self.header+'\n')
f.write(self.header + '\n')
f.write(self.__emit_files(update=update))
f.write('save_project\n')
f.write('close_project\n')
......@@ -148,30 +147,33 @@ mrproper:
tmp = 'libero SCRIPT:{0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
## But do not wait till Libero finish, start displaying output immediately ##
# But do not wait till Libero finish, start displaying output
# immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() != None:
if out == '' and p.poll() is not None:
break
if out != '':
sys.stdout.write(out)
sys.stdout.flush()
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
def create_project(self):
tmp = 'new_project -location {{./{0}}} -name {{{0}}} -hdl {{VHDL}} -family {{ProASIC3}} -die {{{1}}} -package {{{2}}} -speed {{{3}}} -die_voltage {{1.5}}'
self.header = tmp.format(self.filename, self.syn_device.upper(), self.syn_package.upper(), self.syn_grade)
self.header = tmp.format(
self.filename,
self.syn_device.upper(),
self.syn_package.upper(),
self.syn_grade)
def update_project(self):
tmp = 'open_project -file {{{0}/{0}.prjx}}'
self.header = tmp.format(self.filename)
def __emit_files(self, update=False):
link_string = 'create_links {0} {{{1}}}'
enable_string = 'organize_tool_files -tool {{{0}}} -file {{{1}}} -module {{{2}::work}} -input_type {{constraint}}'
......@@ -193,25 +195,28 @@ mrproper:
else:
continue
ret.append(line)
# Second stage: Organizing / activating synthesis constraints (the top module needs to be present!)
# Second stage: Organizing / activating synthesis constraints (the top
# module needs to be present!)
if synthesis_constraints:
line = 'organize_tool_files -tool {SYNTHESIZE} '
for f in synthesis_constraints:
line = line+'-file {'+f.rel_path()+'} '
line = line+'-module {'+self.syn_top+'::work} -input_type {constraint}'
line = line + '-file {' + f.rel_path() + '} '
line = line + \
'-module {' + self.syn_top + '::work} -input_type {constraint}'
ret.append(line)
# Third stage: Organizing / activating compilation constraints (the top module needs to be present!)
# Third stage: Organizing / activating compilation constraints (the top
# module needs to be present!)
if compilation_constraints:
line = 'organize_tool_files -tool {COMPILE} '
for f in compilation_constraints:
line = line+'-file {'+f.rel_path()+'} '
line = line+'-module {'+self.syn_top+'::work} -input_type {constraint}'
line = line + '-file {' + f.rel_path() + '} '
line = line + \
'-module {' + self.syn_top + '::work} -input_type {constraint}'
ret.append(line)
# Fourth stage: set root/top module
line = 'set_root -module {'+self.syn_top+'::work}'
line = 'set_root -module {' + self.syn_top + '::work}'
ret.append(line)
return ('\n'.join(ret))+'\n'
return ('\n'.join(ret)) + '\n'
def supported_files(self, fileset):
from hdlmake.srcfile import SDCFile, PDCFile, SourceFileSet
......@@ -222,4 +227,3 @@ mrproper:
else:
continue
return sup_files
hdlmake/tools/modelsim.py
View file @ 844c0f10
......@@ -33,6 +33,7 @@ MODELSIM_STANDARD_LIBS = ['ieee', 'std', 'altera_mf']
class ToolModelsim(VsimMakefileWriter):
def __init__(self):
super(ToolModelsim, self).__init__()
......@@ -61,13 +62,20 @@ class ToolModelsim(VsimMakefileWriter):
self.vlog_flags.extend(["-modelsimini", "modelsim.ini"])
self.vmap_flags.extend(["-modelsimini", "modelsim.ini"])
if top_module.pool.env["modelsim_path"]:
modelsim_ini_path = os.path.join(top_module.pool.env["modelsim_path"], "..")
modelsim_ini_path = os.path.join(
top_module.pool.env["modelsim_path"],
"..")
else:
modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")
self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
self.additional_deps.append("modelsim.ini")
self.additional_clean.extend(["./modelsim.ini", "transcript", "*.vcd", "*.wlf"])
self.copy_rules["modelsim.ini"] = os.path.join("$(MODELSIM_INI_PATH)", "modelsim.ini")
super(ToolModelsim, self).generate_simulation_makefile(fileset, top_module)
self.additional_clean.extend(
["./modelsim.ini", "transcript", "*.vcd", "*.wlf"])
self.copy_rules["modelsim.ini"] = os.path.join(
"$(MODELSIM_INI_PATH)", "modelsim.ini")
super(
ToolModelsim,
self).generate_simulation_makefile(
fileset,
top_module)
hdlmake/tools/planahead.py
View file @ 844c0f10
......@@ -38,11 +38,10 @@ class ToolPlanAhead(MakefileWriter):
def __init__(self):
super(ToolPlanAhead, self).__init__()
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'PlanAhead',
......@@ -109,24 +108,25 @@ mrproper:
else:
syn_post_cmd = ''
makefile_text = makefile_tmplt.substitute(syn_top=top_mod.manifest_dict["syn_top"],
project_name=top_mod.manifest_dict["syn_project"],
planahead_path=tool_path,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
planahead_sh_path=os.path.join(tool_path, "planAhead"))
makefile_text = makefile_tmplt.substitute(
syn_top=top_mod.manifest_dict["syn_top"],
project_name=top_mod.manifest_dict[
"syn_project"],
planahead_path=tool_path,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
planahead_sh_path=os.path.join(tool_path, "planAhead"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
def generate_remote_synthesis_makefile(self, files, name, cwd, user, server):
def generate_remote_synthesis_makefile(
self, files, name, cwd, user, server):
logging.info("Remote PlanAhead wrapper")
def generate_synthesis_project(self, update=False, tool_version='', top_mod=None, fileset=None):
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
self.properties = []
self.files = []
self.filename = top_mod.manifest_dict["syn_project"]
......@@ -139,21 +139,20 @@ mrproper:
logging.info("No previous project: creating a new one...")
self.create_project()
self.add_initial_properties(top_mod.manifest_dict["syn_device"],
top_mod.manifest_dict["syn_grade"],
top_mod.manifest_dict["syn_package"],
top_mod.manifest_dict["syn_top"])
top_mod.manifest_dict["syn_grade"],
top_mod.manifest_dict["syn_package"],
top_mod.manifest_dict["syn_top"])
self.add_files(fileset)
self.emit()
self.execute()
logging.info("PlanAhead project file generated.")
def emit(self):
f = open(self.tclname, "w")
f.write(self.header+'\n')
f.write(self.header + '\n')
for p in self.properties:
f.write(p.emit()+'\n')
f.write(p.emit() + '\n')
f.write(self.__emit_files())
f.write('update_compile_order -fileset sources_1\n')
f.write('update_compile_order -fileset sim_1\n')
......@@ -164,17 +163,17 @@ mrproper:
tmp = 'planAhead -mode tcl -source {0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
## But do not wait till planahead finish, start displaying output immediately ##
# But do not wait till planahead finish, start displaying output
# immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() != None:
if out == '' and p.poll() is not None:
break
if out != '':
sys.stdout.write(out)
sys.stdout.flush()
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
......@@ -182,28 +181,43 @@ mrproper:
def add_property(self, new_property):
self.properties.append(new_property)
def add_initial_properties(self,
def add_initial_properties(self,
syn_device,
syn_grade,
syn_package,
syn_top):
PAPP = _PlanAheadProjectProperty
self.add_property(PAPP(name='part', value=syn_device+syn_package+syn_grade, objects='current_project'))
self.add_property(PAPP(name='target_language', value='VHDL', objects='current_project'))
self.add_property(PAPP(name='ng.output_hdl_format', value='VHDL', objects='get_filesets sim_1'))
self.add_property(
PAPP(
name='part',
value=syn_device +
syn_package +
syn_grade,
objects='current_project'))
self.add_property(
PAPP(name='target_language',
value='VHDL',
objects='current_project'))
self.add_property(
PAPP(
name='ng.output_hdl_format',
value='VHDL',
objects='get_filesets sim_1'))
# the bitgen b arg generates a raw configuration bitstream
# self.add_property(PAPP(name='steps.bitgen.args.b', value='true', objects='get_runs impl_1'))
self.add_property(PAPP(name='top', value=syn_top, objects='get_property srcset [current_run]'))
# self.add_property(PAPP(name='steps.bitgen.args.b', value='true',
# objects='get_runs impl_1'))
self.add_property(
PAPP(name='top',
value=syn_top,
objects='get_property srcset [current_run]'))
def create_project(self):
tmp = 'create_project {0} ./'
self.header = tmp.format(self.filename)
self.header = tmp.format(self.filename)
def update_project(self):
tmp = 'open_project ./{0}'
self.header = tmp.format(self.filename+'.ppr')
self.header = tmp.format(self.filename + '.ppr')
def __emit_properties(self):
tmp = "set_property {0} {1} [{2}]"
......@@ -211,8 +225,7 @@ mrproper:
for p in self.properties:
line = tmp.format(p.name, p.value, p.objects)
ret.append(line)
return ('\n'.join(ret))+'\n'
return ('\n'.join(ret)) + '\n'
def __emit_files(self):
tmp = "add_files -norecurse {0}"
......@@ -224,8 +237,7 @@ mrproper:
else:
continue
ret.append(line)
return ('\n'.join(ret))+'\n'
return ('\n'.join(ret)) + '\n'
def supported_files(self, fileset):
from hdlmake.srcfile import UCFFile, NGCFile, XMPFile, XCOFile, SourceFileSet
......@@ -238,8 +250,8 @@ mrproper:
return sup_files
class _PlanAheadProjectProperty:
def __init__(self, name=None, value=None, objects=None):
self.name = name
self.value = value
......@@ -249,6 +261,3 @@ class _PlanAheadProjectProperty:
tmp = "set_property {0} {1} [{2}]"
line = tmp.format(self.name, self.value, self.objects)
return(line)
hdlmake/tools/quartus.py
View file @ 844c0f10
This diff is collapsed.
hdlmake/tools/riviera.py
View file @ 844c0f10
......@@ -34,7 +34,7 @@ RIVIERA_STANDARD_LIBS = [
'vtl_dbg', 'assertions', 'ieee_proposed',
'ovm_2_0_3', 'ovm_2_1_2', 'uvm_1_0p1',
'uvm_1_1d', 'uvm', 'osvvm',
]
]
# there are many vendor specific libraries available
# a few of them are listed here
......@@ -61,6 +61,7 @@ RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES)
class ToolRiviera(VsimMakefileWriter):
def __init__(self):
super(ToolRiviera, self).__init__()
self.vcom_flags.append("-2008")
......@@ -85,4 +86,3 @@ class ToolRiviera(VsimMakefileWriter):
from hdlmake.srcfile import SourceFileSet
sup_files = SourceFileSet()
return sup_files
hdlmake/tools/sim_makefile_support.py
View file @ 844c0f10
This diff is collapsed.
hdlmake/tools/vivado.py
View file @ 844c0f10
......@@ -37,11 +37,10 @@ class ToolVivado(MakefileWriter):
def __init__(self):
super(ToolVivado, self).__init__()
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'vivado',
......@@ -106,24 +105,25 @@ mrproper:
else:
syn_post_cmd = ''
makefile_text = makefile_tmplt.substitute(syn_top=top_mod.manifest_dict["syn_top"],
project_name=top_mod.manifest_dict["syn_project"],
planahead_path=tool_path,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
vivado_sh_path=os.path.join(tool_path, "vivado"))
makefile_text = makefile_tmplt.substitute(
syn_top=top_mod.manifest_dict["syn_top"],
project_name=top_mod.manifest_dict[
"syn_project"],
planahead_path=tool_path,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
vivado_sh_path=os.path.join(tool_path, "vivado"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
def generate_remote_synthesis_makefile(self, files, name, cwd, user, server):
def generate_remote_synthesis_makefile(
self, files, name, cwd, user, server):
logging.info("Remote Vivado wrapper")
def generate_synthesis_project(self, update=False, tool_version='', top_mod=None, fileset=None):
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
self.properties = []
self.files = []
self.filename = top_mod.manifest_dict["syn_project"]
......@@ -136,21 +136,20 @@ mrproper:
logging.info("No previous project: creating a new one...")
self.create_project()
self.add_initial_properties(top_mod.manifest_dict["syn_device"],
top_mod.manifest_dict["syn_grade"],
top_mod.manifest_dict["syn_package"],
top_mod.manifest_dict["syn_top"])
top_mod.manifest_dict["syn_grade"],
top_mod.manifest_dict["syn_package"],
top_mod.manifest_dict["syn_top"])
self.add_files(fileset)
self.emit()
self.execute()
logging.info("Vivado project file generated.")
def emit(self):
f = open(self.tclname, "w")
f.write(self.header+'\n')
f.write(self.header + '\n')
for p in self.properties:
f.write(p.emit()+'\n')
f.write(p.emit() + '\n')
f.write(self.__emit_files())
f.write('update_compile_order -fileset sources_1\n')
f.write('update_compile_order -fileset sim_1\n')
......@@ -161,17 +160,17 @@ mrproper:
tmp = 'vivado -mode tcl -source {0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
## But do not wait till Vivado finish, start displaying output immediately ##
# But do not wait till Vivado finish, start displaying output
# immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() != None:
if out == '' and p.poll() is not None:
break
if out != '':
sys.stdout.write(out)
sys.stdout.flush()
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
......@@ -179,30 +178,43 @@ mrproper:
def add_property(self, new_property):
self.properties.append(new_property)
def add_initial_properties(self,
def add_initial_properties(self,
syn_device,
syn_grade,
syn_package,
syn_top):
PAPP = _VivadoProjectProperty
self.add_property(PAPP(name='part', value=syn_device+syn_package+syn_grade, objects='current_project'))
# self.add_property(PAPP(name='board_part', value='em.avnet.com:microzed_7010:part0:1.0', objects='current_project'))
self.add_property(PAPP(name='target_language', value='VHDL', objects='current_project'))
self.add_property(
PAPP(
name='part',
value=syn_device +
syn_package +
syn_grade,
objects='current_project'))
# self.add_property(PAPP(name='board_part',
# value='em.avnet.com:microzed_7010:part0:1.0',
# objects='current_project'))
self.add_property(
PAPP(name='target_language',
value='VHDL',
objects='current_project'))
# self.add_property(PAPP(name='ng.output_hdl_format', value='VHDL', objects='get_filesets sim_1'))
# the bitgen b arg generates a raw configuration bitstream
# self.add_property(PAPP(name='steps.bitgen.args.b', value='true', objects='get_runs impl_1'))
self.add_property(PAPP(name='top', value=syn_top, objects='get_property srcset [current_run]'))
# self.add_property(PAPP(name='steps.bitgen.args.b', value='true',
# objects='get_runs impl_1'))
self.add_property(
PAPP(name='top',
value=syn_top,
objects='get_property srcset [current_run]'))
def create_project(self):
tmp = 'create_project {0} ./'
self.header = tmp.format(self.filename)
self.header = tmp.format(self.filename)
def update_project(self):
tmp = 'open_project ./{0}'
self.header = tmp.format(self.filename+'.xpr')
self.header = tmp.format(self.filename + '.xpr')
def __emit_properties(self):
tmp = "set_property {0} {1} [{2}]"
......@@ -210,8 +222,7 @@ mrproper:
for p in self.properties:
line = tmp.format(p.name, p.value, p.objects)
ret.append(line)
return ('\n'.join(ret))+'\n'
return ('\n'.join(ret)) + '\n'
def __emit_files(self):
tmp = "add_files -norecurse {0}"
......@@ -226,7 +237,7 @@ mrproper:
else:
continue
ret.append(line)
return ('\n'.join(ret))+'\n'
return ('\n'.join(ret)) + '\n'
def supported_files(self, fileset):
from hdlmake.srcfile import UCFFile, NGCFile, XMPFile, XCOFile
......@@ -234,21 +245,21 @@ mrproper:
sup_files = SourceFileSet()
for f in fileset:
if (
(isinstance(f, UCFFile)) or
(isinstance(f, NGCFile)) or
(isinstance(f, XMPFile)) or
(isinstance(f, XCOFile)) or
(isinstance(f, BDFile)) or
(isinstance(f, TCLFile))
):
(isinstance(f, UCFFile)) or
(isinstance(f, NGCFile)) or
(isinstance(f, XMPFile)) or
(isinstance(f, XCOFile)) or
(isinstance(f, BDFile)) or
(isinstance(f, TCLFile))
):
sup_files.add(f)
else:
continue
return sup_files
class _VivadoProjectProperty:
def __init__(self, name=None, value=None, objects=None):
self.name = name
self.value = value
......@@ -258,4 +269,3 @@ class _VivadoProjectProperty:
tmp = "set_property {0} {1} [{2}]"
line = tmp.format(self.name, self.value, self.objects)
return(line)
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