Commit 85f8c39c authored by Christos Gentsos's avatar Christos Gentsos

Organize HDL file extensions in sets and use them in the CXF parser

parent 80e7a57b
......@@ -22,6 +22,7 @@
from __future__ import absolute_import
import re
import os
import logging
from xml.etree import ElementTree as ET
......@@ -29,6 +30,7 @@ from xml.etree import ElementTree as ET
from .new_dep_solver import DepParser
from .dep_file import DepRelation
from ..sourcefiles.srcfile import create_source_file
from ..sourcefiles.srcfile import VHDL_EXTENSIONS, VERILOG_EXTENSIONS, SV_EXTENSIONS
class CXFParser(DepParser):
"""Class providing the Microsemi CXF parser"""
......@@ -63,7 +65,8 @@ class CXFParser(DepParser):
# gather the list of source files
for i in xmlET.iter(ns+'file'):
for ii in i.iter(ns+'name'):
if ii.text.endswith(('.vhd', '.cxf')):
_, extension = os.path.splitext(ii.text)
if extension[1:] in VHDL_EXTENSIONS + VERILOG_EXTENSIONS + SV_EXTENSIONS + ('sdc', 'cxf'):
dep_file.included_files.add(ii.text)
if not module_name is None:
......
......@@ -323,6 +323,23 @@ ALTERA_FILE_DICT = {
'gdf': GDFFile}
VHDL_EXTENSIONS = (
'vhd',
'vhdl',
'vho')
VERILOG_EXTENSIONS = (
'v',
'vh',
'vo',
'vm')
SV_EXTENSIONS = (
'sv',
'svh')
def create_source_file(path, module, library=None, include_dirs=None):
"""Function that analyzes the given arguments and returns a new HDL source
file of the appropriated type"""
......@@ -334,16 +351,16 @@ def create_source_file(path, module, library=None, include_dirs=None):
extension = extension[1:]
logging.debug("add file " + path)
if extension in ['vhd', 'vhdl', 'vho']:
if extension in VHDL_EXTENSIONS:
new_file = VHDLFile(path=path,
module=module,
library=library)
elif extension in ['v', 'vh', 'vo', 'vm']:
elif extension in VERILOG_EXTENSIONS:
new_file = VerilogFile(path=path,
module=module,
library=library,
include_dirs=include_dirs)
elif extension == 'sv' or extension == 'svh':
elif extension in SV_EXTENSIONS:
new_file = SVFile(path=path,
module=module,
library=library,
......
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