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Hdlmake
Commit 87521299 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Refactoring: focus on ModuleSimulation.py

parent 31f8fa67
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Showing with 129 additions and 43 deletions
hdlmake/module/__init__.py
View file @ 87521299
......@@ -3,5 +3,5 @@ from .synthesis import ModuleSynthesis
from .simulation import ModuleSimulation
from .content import ModuleContent
from .altera import ModuleAltera
from .module import Module
from .module import Module, ModuleArgs
hdlmake/module/core.py
View file @ 87521299
......@@ -35,9 +35,14 @@ class ModuleConfig(object):
"""Get the fetchto folder for the module"""
return os.path.dirname(self.path)
def init_config(self, parent, url, source, fetchto):
def init_config(self, module_args):
"""This initializes the module configuration.
The function is executed by Module constructor"""
parent = module_args.parent
url = module_args.url
source = module_args.source
fetchto = module_args.fetchto
self.source = source
self.parent = parent
......
hdlmake/module/module.py
View file @ 87521299
......@@ -36,6 +36,26 @@ from hdlmake.module import (ModuleSynthesis,
ModuleSimulation, ModuleContent, ModuleAltera)
class ModuleArgs(object):
"""This class is just a container for the main Module args"""
def __init__(self):
self.parent = None
self.url = None
self.source = None
self.fetchto = None
def set_args(self, parent, url, source, fetchto):
"""Set the module arguments"""
self.parent = parent
self.url = url
self.source = source
self.fetchto = fetchto
def get_args(self):
"""Get the module arguments"""
return self.parent, self.url, self.source, self.fetchto
class Module(ModuleSynthesis,
ModuleSimulation, ModuleContent, ModuleAltera):
"""
......@@ -43,13 +63,15 @@ class Module(ModuleSynthesis,
providing the modular behavior allowing for structured designs.
"""
def __init__(self, parent, url, source, fetchto):
def __init__(self, module_args, pool):
"""Calculate and initialize the origin attributes: path, source..."""
assert url is not None
assert source is not None
assert module_args.url is not None
assert module_args.source is not None
super(Module, self).__init__()
self.init_config(parent, url, source, fetchto)
self.init_config(module_args)
self.set_pool(pool)
self.module_args = ModuleArgs()
self.module_args = module_args
def __str__(self):
......@@ -104,10 +126,10 @@ class Module(ModuleSynthesis,
from hdlmake.srcfile import VerilogFile, VHDLFile
for file_aux in self.files:
if isinstance(file_aux, VerilogFile):
file_aux.vsim_opt = self.vsim_opt
file_aux.vsim_opt = self.sim_opt.vsim_opt
file_aux.include_dirs = self.include_dirs
elif isinstance(file_aux, VHDLFile):
file_aux.vcom_opt = self.vcom_opt
file_aux.vcom_opt = self.sim_opt.vcom_opt
file_aux.include_dirs = self.include_dirs
......@@ -134,6 +156,10 @@ class Module(ModuleSynthesis,
if self.path is None:
raise RuntimeError()
logging.debug("""
***********************************************************
PARSE START: %s
***********************************************************""", self.path)
manifest_parser = ManifestParser()
......@@ -166,4 +192,10 @@ class Module(ModuleSynthesis,
for module_aux in self.submodules():
module_aux.parse_manifest()
logging.debug("""
***********************************************************
PARSE END: %s
***********************************************************
""", self.path)
hdlmake/module/simulation.py
View file @ 87521299
"""This module is in charge of providing everything related with simulation
at the Module level"""
import os
import logging
from .core import ModuleCore
from hdlmake.util import path as path_mod
class SimulatorOptions(object):
"""Class providing a storage for simulator options"""
def __init__(self):
self.vsim_opt = None
self.vmap_opt = None
self.vlog_opt = None
self.vcom_opt = None
self.iverilog_opt = None
def set_standard_options(self, vsim_opt, vmap_opt, vlog_opt, vcom_opt):
"""Set the standard simulator options, i.e. vsim, vmap, vlog, vcom"""
self.vsim_opt = vsim_opt
self.vmap_opt = vmap_opt
self.vlog_opt = vlog_opt
self.vcom_opt = vcom_opt
def set_iverilog_options(self, iverilog_opt):
"""Set the specific options for Icarus Verilog"""
self.iverilog_opt = iverilog_opt
class ModuleSimulation(ModuleCore):
"""This Class provides the HDLMake properties and methods
the Module requires for the simulation action"""
def __init__(self):
# Manifest Simulation Properties
self.sim_top = None
self.sim_tool = None
self.sim_pre_script = None
self.sim_post_script = None
self.sim_pre_cmd = None
self.sim_post_cmd = None
self.sim_only_files = None
self.vsim_opt = None
self.vmap_opt = None
self.vlog_opt = None
self.vcom_opt = None
self.iverilog_opt = None
self.sim_opt = SimulatorOptions()
# Includes Manifest Properties
self.include_dirs = None
super(ModuleSimulation, self).__init__()
def process_manifest(self):
"""Method that processes the simulation section in the manifest"""
self._process_manifest_simulation()
self._process_manifest_includes()
super(ModuleSimulation, self).process_manifest()
def _process_manifest_simulation(self):
"""Private method that processes options and universal sim keys"""
from hdlmake.srcfile import SourceFileSet
# Simulation properties
self.sim_tool = self.manifest_dict["sim_tool"]
......@@ -32,35 +59,51 @@ class ModuleSimulation(ModuleCore):
self.sim_pre_cmd = self.manifest_dict["sim_pre_cmd"]
self.sim_post_cmd = self.manifest_dict["sim_post_cmd"]
self.vmap_opt = self.manifest_dict["vmap_opt"]
self.vcom_opt = self.manifest_dict["vcom_opt"]
self.vsim_opt = self.manifest_dict["vsim_opt"]
self.vlog_opt = self.manifest_dict["vlog_opt"]
self.iverilog_opt = self.manifest_dict["iverilog_opt"]
self.sim_opt.vsim_opt = self.manifest_dict["vsim_opt"]
self.sim_opt.vmap_opt = self.manifest_dict["vmap_opt"]
self.sim_opt.vlog_opt = self.manifest_dict["vlog_opt"]
self.sim_opt.vcom_opt = self.manifest_dict["vcom_opt"]
self.sim_opt.set_standard_options(
self.manifest_dict["vsim_opt"],
self.manifest_dict["vmap_opt"],
self.manifest_dict["vlog_opt"],
self.manifest_dict["vcom_opt"]
)
self.sim_opt.set_iverilog_options(self.manifest_dict["iverilog_opt"])
if len(self.manifest_dict["sim_only_files"]) == 0:
self.sim_only_files = SourceFileSet()
else:
self.manifest_dict["sim_only_files"] = path_mod.flatten_list(self.manifest_dict["sim_only_files"])
paths = self._make_list_of_paths(self.manifest_dict["sim_only_files"])
self.sim_only_files = self._create_file_list_from_paths(paths=paths)
self.manifest_dict["sim_only_files"] = path_mod.flatten_list(
self.manifest_dict["sim_only_files"])
paths = self._make_list_of_paths(
self.manifest_dict["sim_only_files"])
self.sim_only_files = self._create_file_list_from_paths(
paths=paths)
def _process_manifest_includes(self):
"""Private method that processes the included directory list"""
# Include dirs
self.include_dirs = []
if self.manifest_dict["include_dirs"] is not None:
if isinstance(self.manifest_dict["include_dirs"], basestring):
ll = os.path.relpath(os.path.abspath(os.path.join(self.path, self.manifest_dict["include_dirs"])))
self.include_dirs.append(ll)
dir_list = path_mod.compose(
self.path, self.manifest_dict["include_dirs"])
self.include_dirs.append(dir_list)
else:
ll = map(lambda x: os.path.relpath(os.path.abspath(os.path.join(self.path, x))),
self.manifest_dict["include_dirs"])
self.include_dirs.extend(ll)
dir_list = [path_mod.compose(self.path, x) for
x in self.manifest_dict["include_dirs"]]
self.include_dirs.extend(dir_list)
# Analyze included dirs and report if any issue is found
for dir_ in self.include_dirs:
if path_mod.is_abs_path(dir_):
logging.warning("%s contains absolute path to an include directory: %s" % (self.path, dir_))
logging.warning(
"%s contains absolute path to an include directory: %s",
self.path, dir_)
if not os.path.exists(dir_):
logging.warning(self.path + " has an unexisting include directory: " + dir_)
logging.warning(self.path +
" has an unexisting include directory: " + dir_)
hdlmake/module_pool.py
View file @ 87521299
......@@ -84,15 +84,14 @@ class ModulePool(list):
NOTE: the first module added to the pool will become the top_module!.
"""
from .module import Module
from .module import Module, ModuleArgs
self._deps_solved = False
new_module = Module(parent=parent,
url=url, source=source,
fetchto=fetchto)
new_module_args = ModuleArgs()
new_module_args.set_args(parent, url, source, fetchto)
new_module = Module(new_module_args, self)
if not self.__contains(new_module):
new_module.set_pool(self)
self._add(new_module)
if not self.top_module:
self.top_module = new_module
......
hdlmake/tools/common/sim_makefile_support.py
View file @ 87521299
......@@ -75,10 +75,10 @@ class VsimMakefileWriter(MakefileWriter):
mkdir_command = "mkdir -p"
slash_char = "/"
self.vlog_flags.append(self.__get_rid_of_vsim_incdirs(top_module.vlog_opt))
self.vcom_flags.append(top_module.vcom_opt)
self.vmap_flags.append(top_module.vmap_opt)
self.vsim_flags.append(top_module.vsim_opt)
self.vlog_flags.append(self.__get_rid_of_vsim_incdirs(top_module.sim_opt.vlog_opt))
self.vcom_flags.append(top_module.sim_opt.vcom_opt)
self.vmap_flags.append(top_module.sim_opt.vmap_opt)
self.vsim_flags.append(top_module.sim_opt.vsim_opt)
tmp = """## variables #############################
PWD := $(shell pwd)
......
hdlmake/tools/isim/isim.py
View file @ 87521299
......@@ -87,7 +87,7 @@ XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) + """
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.vlog_opt) + """
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.sim_opt.vlog_opt) + """
"""
make_preambule_p2 = string.Template("""## rules #################################
local: sim_pre_cmd simulation sim_post_cmd
......
hdlmake/tools/iverilog/iverilog.py
View file @ 87521299
......@@ -125,8 +125,8 @@ mrproper: clean
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
if top_module.iverilog_opt:
iverilog_opt = top_module.iverilog_opt
if top_module.sim_opt.iverilog_opt:
iverilog_opt = top_module.sim_opt.iverilog_opt
else:
iverilog_opt = ''
......
hdlmake/util/path.py
View file @ 87521299
......@@ -130,6 +130,13 @@ def rel2abs(path, base=None):
return os.path.abspath(retval)
def compose(path, base=None):
"""Get the relative path composition of the provided path"""
if base is None:
base = os.getcwd()
return os.path.relpath(os.path.abspath(os.path.join(base, path)))
def search_for_manifest(search_path):
"""
Look for manifest in the given folder
......
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