Do not enable SystemVerilog 2005 in Quartus, but support syn_properties in the Manifest

parent 2f5ab537
......@@ -1201,6 +1201,41 @@ If you want to use a different Intel Quartus version, you will need to fix the I
-- Retrieval info: <generic name="number_of_reconfig_interfaces" value="2" />
-- Retrieval info: <generic name="gui_split_sizes" value="" />
If you want to regenerate the Quartus project by using your **custom Quartus properties**, you may replace the provided ```` with the following one and edit it accordingly. Note that this will generate ``set_global_assignment`` statements in which the first input specify the ``name`` of the property and the second input its value. As an example, we force the VHDL and Verilog input version and optimize the synthesis for speed:
.. code-block:: python
target = "altera"
action = "synthesis"
syn_family = "Arria V"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "vfchd_wr_ref_top"
syn_project = "vfchd_wr_ref"
syn_tool = "quartus"
syn_properties = [
["optimization_technique", "speed"]]
quartus_preflow = "quartus_preflow.tcl"
files = [
modules = {
"local" : [
Mentor Modelsim
......@@ -200,10 +200,10 @@ class ToolQuartus(ToolSyn):
{'name_type': 'TOP_LEVEL_ENTITY',
'name': '\\"$(TOP_MODULE)\\"'}))
{'name_type': 'VERILOG_INPUT_VERSION',
'name': 'SYSTEMVERILOG_2005'}))
for user_property in self.manifest_dict.get("syn_properties", []):
{'name_type': user_property[0],
'name': user_property[1]}))
for inc in self.manifest_dict.get("include_dirs", []):
{'name_type': 'SEARCH_PATH',
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment