Clean the not officially supported tests

parent 605c11b8
*~
work
certe_dump.xml
modelsim.ini
transcript
vsim.wlf
The hdlmake should be called from: sim/tests/
\ No newline at end of file
include_dirs = "include"
files = "ipcore.sv"
// -*- Mode: Verilog -*-
// Filename : ipcoreInclude.sv
// Description : Example ipcoreinclude
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 11:01:31 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 11:01:31 2014
// Update Count : 0
// Status : Unknown, Use with caution!
module ipcoreInclude;
endmodule // ipcoreinclude
// -*- Mode: Verilog -*-
// Filename : ipcore.sv
// Description : Example ipcore
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 11:00:12 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 11:00:12 2014
// Update Count : 0
// Status : Unknown, Use with caution!
`include "ipcoreInclude.sv"
module ipcore;
ipcoreInclude incl();
endmodule // ipcore
/*****************************************************************************
*
* Copyright 2008 Mentor Graphics Corporation
* All Rights Reserved.
*
* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
* MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
*
*****************************************************************************/
`ifdef MVC_NO_DEPRECATED
// This entire file is deprecated. Testbenches should no longer even include this file.
`__FILE__
`else
`include "uvm_macros.svh"
`define get_interface( _if ) _if
`define DEFINE_VIF_TYPE( IF_NAME ) virtual mgc_``IF_NAME
`define mvc_report_info( id , mess ) `uvm_info( id , mess , UVM_MEDIUM )
`define mvc_report_warning( id , mess ) `uvm_warning( id , mess )
`define mvc_report_error( id , mess ) `uvm_error( id , mess )
`define mvc_report_fatal( id , mess ) `uvm_fatal( id , mess )
`ifdef MODEL_TECH
`undef m_uvm_get_type_name_func
`define m_uvm_get_type_name_func(T) \
`uvm_get_type_name_func(T)
`define uvm_get_type_name_func(T) \
localparam string type_name = `"T`"; \
virtual function string get_type_name (); \
return type_name; \
endfunction
`define mvc_get_type_name_func( specialization ) \
localparam type_name = specialization; \
virtual function string get_type_name(); \
return type_name; \
endfunction \
//
// The name is a user supplied string unique to this specialization T of a parameterized class
//
`define mvc_object_param_utils( T , name ) \
`uvm_object_registry(T, name) \
`mvc_get_type_name_func( name ) \
`uvm_field_utils_begin(T) \
`uvm_object_utils_end
//
// The name is a user supplied string unique to this specialization T of a parameterized class
//
`define mvc_component_param_utils( T , name ) \
`uvm_component_registry(T, name) \
`mvc_get_type_name_func( name ) \
`uvm_field_utils_begin(T) \
`uvm_object_utils_end
`else
`define mvc_object_param_utils( T , name ) \
`uvm_object_param_utils( T )
`define mvc_component_param_utils( T , name ) \
`uvm_component_param_utils( T )
`endif
`endif
\ No newline at end of file
/*****************************************************************************
*
* Copyright 2007-2014 Mentor Graphics Corporation
* All Rights Reserved.
*
* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
* MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
*
*****************************************************************************/
package mvc_pkg;
endpackage
include_dirs = "./include"
files = ["include/includeModuleSV.sv",
"include/includeModuleVHDL.vhdl",
"include/includeModuleAVHDL.vhdl",
"include/includeModuleBVHDL.vhdl",
"RTL_SVPackage.sv",
"RTLTopModuleSV.sv",
"RTLTopModuleVerilogSimulationModel.vo",
"RTLTopModuleVHDL.vhdl"]
modules = { "local" : ["../ipcores/ipcore"]}
// -*- Mode: Verilog -*-
// Filename : RTLTopModuleSV.sv
// Description : RTL top module (DUT).
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:50:28 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:50:28 2014
// Update Count : 0
// Status : Unknown, Use with caution!
module RTLTopModuleSV;
logic l1a;
initial
l1a <= RTL_SVPackage::CONST;
includeModuleSV incl();
ipcore ip();
endmodule // RTLTopModuleSV
-------------------------------------------------------------------------------
-- Title : RTLTopModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : RTLTopModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RTLTopModuleVHDL is
end entity RTLTopModuleVHDL;
architecture Behavioral of RTLTopModuleVHDL is
component includeModuleVHDL is
end component;
signal probe : STD_LOGIC;
begin -- architectureecture Behavioral
probe <= '1';
include_module : includeModuleVHDL;
a : entity work.includeModuleAVHDL;
GEN : for i in 0 to 3 generate
B : entity work.includeModuleBVHDL;
end generate;
end architecture Behavioral;
module RTLTopModuleVerilogSimulationModel;
endmodule
package RTL_SVPackage;
localparam CONST = 0;
endpackage // RTL_SVPackage
-------------------------------------------------------------------------------
-- Title : includeModuleAVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleAVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleAVHDL is
end entity includeModuleAVHDL;
architecture Behavioral of includeModuleAVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
-------------------------------------------------------------------------------
-- Title : includeModuleBVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleBVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleBVHDL is
end entity includeModuleBVHDL;
architecture Behavioral of includeModuleBVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
// -*- Mode: Verilog -*-
// Filename : includeModuleSV.sv
// Description : Included submodule
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:51:41 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:51:41 2014
// Update Count : 0
// Status : Unknown, Use with caution!
module includeModuleSV;
endmodule // includeModuleSV
-------------------------------------------------------------------------------
-- Title : includeModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleVHDL is
end entity includeModuleVHDL;
architecture Behavioral of includeModuleVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
// -*- Mode: Verilog -*-
// Filename : Env_pkg.sv
// Description : Package containing environment's components.
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:48:26 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:48:26 2014
// Update Count : 0
// Status : Unknown, Use with caution!
`ifndef ENG_PKG_SV
`define ENG_PKG_SV
`include <mvc_macros.svh>
`include <mvc_pkg.sv>
package Env_pkg;
import uvm_pkg::*;
`include <uvm_macros.svh>
`include "env.sv"
endpackage // Env_pkg
`endif
// -*- Mode: Verilog -*-
// Filename : env.sv
// Description : Example UVM environment
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 11:04:56 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 11:04:56 2014
// Update Count : 0
// Status : Unknown, Use with caution!
class env extends uvm_env;
`uvm_component_utils_begin(env)
`uvm_component_utils_end
//Function: new
//Creates a new <env> with the given ~name~ and ~parent~.
function new(string name="", uvm_component parent);
super.new(name, parent);
endfunction // new
endclass // env
// -*- Mode: Verilog -*-
// Filename : top.sv
// Description : Top simulation module.
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:47:27 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:47:27 2014
// Update Count : 0
// Status : Unknown, Use with caution!
module automatic top;
timeunit 1ns;
timeprecision 1ps;
RTLTopModuleSV sv();
RTLTopModuleVHDL vhdl();
RTLTopModuleVerilogSimulationModel vsm();
initial
run_test("genericTest");
endmodule // top
// -*- Mode: Verilog -*-
// Filename : sequence.sv
// Description : An example sequence item.
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:47:00 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:47:00 2014
// Update Count : 0
// Status : Unknown, Use with caution!
class sequenceA extends uvm_sequence_item;
`uvm_object_utils_begin(sequenceA)
`uvm_object_utils_end
//Function: new
//Creates a new <sequenceA> with the given ~name~..
function new(string name="");
super.new(name);
endfunction // new
endclass // sequenceA
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
MODELSIM_INI_PATH := /opt/questa_sv_afv_10.4/questasim//bin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC := ../../ipcores/ipcore/ipcore.sv \
../../rtl/RTL_SVPackage.sv \
src/genericTest.sv \
../../rtl/RTLTopModuleVerilogSimulationModel.vo \
../../rtl/include/includeModuleSV.sv \
../../rtl/RTLTopModuleSV.sv \
VERILOG_OBJ := work/ipcore/.ipcore_sv \
work/RTL_SVPackage/.RTL_SVPackage_sv \
work/genericTest/.genericTest_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
work/includeModuleSV/.includeModuleSV_sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
VHDL_SRC := ../../rtl/include/includeModuleBVHDL.vhdl \
../../rtl/include/includeModuleVHDL.vhdl \
../../rtl/include/includeModuleAVHDL.vhdl \
../../rtl/RTLTopModuleVHDL.vhdl \
VHDL_OBJ := work/includeModuleBVHDL/.includeModuleBVHDL_vhdl \
work/includeModuleVHDL/.includeModuleVHDL_vhdl \
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl \
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl \
LIBS := work
LIB_IND := work/.work
## rules #################################
local: sim_pre_cmd simulation sim_post_cmd
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
sim_pre_cmd:
sim_post_cmd:
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
clean:
rm -rf ./modelsim.ini $(LIBS) transcript *.vcd *.wlf
.PHONY: clean sim_pre_cmd sim_post_cmd simulation
work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/ipcore/.ipcore_sv: ../../ipcores/ipcore/ipcore.sv \
../../ipcores/ipcore/include/ipcoreInclude.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../ipcores/ipcore/include+../../ipcores/ipcore $<
@mkdir -p $(dir $@) && touch $@
work/RTL_SVPackage/.RTL_SVPackage_sv: ../../rtl/RTL_SVPackage.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/genericTest/.genericTest_sv: src/genericTest.sv \
../environment/env.sv \
../sequences/sequence.sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
src/FullTest_pkg.sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
../environment/top.sv \
../environment/Env_pkg.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../environment+../sequences+src +incdir+../../mvc//questa_mvc_src/sv+../../mvc/questa_mvc_src/sv/mvc_base+../../mvc/include+../../uvm-1.1d/src $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo: ../../rtl/RTLTopModuleVerilogSimulationModel.vo
vlog -work work $(VLOG_FLAGS) +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleSV/.includeModuleSV_sv: ../../rtl/include/includeModuleSV.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl/include $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleSV/.RTLTopModuleSV_sv: ../../rtl/RTLTopModuleSV.sv \
work/ipcore/.ipcore_sv \
work/includeModuleSV/.includeModuleSV_sv \
work/RTL_SVPackage/.RTL_SVPackage_sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl: ../../rtl/include/includeModuleBVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleVHDL/.includeModuleVHDL_vhdl: ../../rtl/include/includeModuleVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl: ../../rtl/include/includeModuleAVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl \
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl \
work/includeModuleVHDL/.includeModuleVHDL_vhdl \
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
action = "simulation"
include_dirs = [ "../environment/",
"../sequences/"]
vlog_opt = '+incdir+' + \
'../../mvc//questa_mvc_src/sv+' + \
'../../mvc/questa_mvc_src/sv/mvc_base+' + \
'../../mvc/include+' +\
'../../uvm-1.1d/src'
top_module = "top"
sim_tool = "modelsim"
files = ["src/genericTest.sv"]
modules = { "local" : ["../../rtl"] }
quit -sim
make
vsim -classdebug -uvmcontrol=all -msgmode both -t ps -novopt work.top
run -all
// -*- Mode: Verilog -*-
// Filename : FullTest_pkg.sv
// Description : The package contains custom sequences
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:35:56 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:35:56 2014
// Update Count : 0
// Status : Unknown, Use with caution!
`ifndef FULLTEST_PKG_SV
`define FULLTEST_PKG_SV
//Title: FullTest_pkg
//Package: FullTest_pkg
//The package contains sequences available for full tests.
package FullTest_pkg;
import uvm_pkg::*;
`include <uvm_macros.svh>
`include "sequence.sv"
endpackage // FullTest_pkg
`endif
// -*- Mode: Verilog -*-
// Filename : genericTest.sv
// Description : The generic test
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:34:01 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:34:01 2014
// Update Count : 0
// Status : Unknown, Use with caution!
timeunit 1ns;
timeprecision 1ps;
import uvm_pkg::*;
`include <uvm_macros.svh>
`include "Env_pkg.sv"
`include "FullTest_pkg.sv"
`include "top.sv"
import Env_pkg::*;
import FullTest_pkg::*;
//Class: genericTest
class genericTest extends uvm_test;
env i_env;