Maintenance scheduled 24th July -- expect downtime along that day

Commit aabe6c84 authored by Adrian Fiergolski's avatar Adrian Fiergolski

Disable optimisations in order to have visibility of counter's signal.

parent 9bf38895
......@@ -2,7 +2,7 @@ action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"
sim_post_cmd = "vsim -novopt -do ../vsim.do -i counter_tb"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
......
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