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Hdlmake
Commits
b0ccccc6
Commit
b0ccccc6
authored
Apr 03, 2014
by
Wesley W. Terpstra
Committed by
Pawel Szostek
Apr 03, 2014
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Plain Diff
altera: support pre/post-flow scripts
Signed-off-by:
Pawel Szostek
<
pawel.szostek@cern.ch
>
parent
764797fe
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Showing
3 changed files
with
27 additions
and
5 deletions
+27
-5
quartus_project.py
hdlmake/action/quartus_project.py
+4
-4
manifest_parser.py
hdlmake/manifest_parser.py
+4
-0
module.py
hdlmake/module.py
+19
-1
No files found.
hdlmake/action/quartus_project.py
View file @
b0ccccc6
...
...
@@ -56,8 +56,8 @@ class GenerateQuartusProject(Action):
top_mod
.
syn_grade
,
top_mod
.
syn_package
,
top_mod
.
syn_top
)
prj
.
preflow
=
None
prj
.
postflow
=
None
prj
.
preflow
=
top_mod
.
quartus_preflow
prj
.
postflow
=
top_mod
.
quartus_postflow
prj
.
emit
()
...
...
@@ -68,7 +68,7 @@ class GenerateQuartusProject(Action):
fileset
.
add
(
non_dependable
)
prj
=
QuartusProject
(
top_mod
.
syn_project
)
prj
.
read
()
prj
.
preflow
=
None
prj
.
postflow
=
None
prj
.
preflow
=
top_mod
.
quartus_preflow
prj
.
postflow
=
top_mod
.
quartus_postflow
prj
.
add_files
(
fileset
)
prj
.
emit
()
hdlmake/manifest_parser.py
View file @
b0ccccc6
...
...
@@ -70,6 +70,10 @@ class ManifestParser(ConfigParser):
self
.
add_option
(
'force_tool'
,
default
=
None
,
help
=
"Force certain version of a tool, e.g. 'ise < 13.2' or 'iverilog == 0.9.6"
,
type
=
''
)
self
.
add_delimiter
()
self
.
add_option
(
'quartus_preflow'
,
default
=
None
,
help
=
"Quartus pre-flow script file"
,
type
=
''
)
self
.
add_option
(
'quartus_postflow'
,
default
=
None
,
help
=
"Quartus post-flow script file"
,
type
=
''
)
self
.
add_delimiter
()
self
.
add_option
(
'include_dirs'
,
default
=
None
,
help
=
"Include dirs for Verilog sources"
,
type
=
[])
self
.
add_type
(
'include_dirs'
,
type
=
""
)
...
...
hdlmake/module.py
View file @
b0ccccc6
...
...
@@ -75,6 +75,8 @@ class Module(object):
self
.
vlog_opt
=
None
self
.
vcom_opt
=
None
self
.
revision
=
None
self
.
quartus_preflow
=
None
self
.
quartus_postflow
=
None
self
.
_files
=
None
self
.
manifest
=
None
self
.
incl_makefiles
=
[]
...
...
@@ -224,7 +226,7 @@ class Module(object):
self
.
manifest_dict
=
opt_map
def
process_manifest
(
self
):
from
srcfile
import
VerilogFile
,
VHDLFile
,
SourceFileSet
from
srcfile
import
TCLFile
,
VerilogFile
,
VHDLFile
,
SourceFileSet
if
self
.
isprocessed
is
True
:
return
if
self
.
manifest_dict
is
None
:
...
...
@@ -393,6 +395,22 @@ class Module(object):
self
.
syn_project
=
self
.
manifest_dict
[
"syn_project"
]
self
.
syn_top
=
self
.
manifest_dict
[
"syn_top"
]
if
self
.
manifest_dict
[
"quartus_preflow"
]
!=
None
:
path
=
path_mod
.
rel2abs
(
self
.
manifest_dict
[
"quartus_preflow"
],
self
.
path
);
if
not
os
.
path
.
exists
(
path
):
p
.
error
(
"quartus_preflow file listed in "
+
self
.
manifest
.
path
+
" doesn't exist: "
+
path
+
".
\n
Exiting."
)
quit
()
self
.
quartus_preflow
=
TCLFile
(
path
)
if
self
.
manifest_dict
[
"quartus_postflow"
]
!=
None
:
path
=
path_mod
.
rel2abs
(
self
.
manifest_dict
[
"quartus_postflow"
],
self
.
path
);
if
not
os
.
path
.
exists
(
path
):
p
.
error
(
"quartus_postflow file listed in "
+
self
.
manifest
.
path
+
" doesn't exist: "
+
path
+
".
\n
Exiting."
)
quit
()
self
.
quartus_postflow
=
TCLFile
(
path
)
self
.
isparsed
=
True
self
.
isprocessed
=
True
...
...
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