Commit b0ccccc6 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra Committed by Pawel Szostek

altera: support pre/post-flow scripts

Signed-off-by: 's avatarPawel Szostek <pawel.szostek@cern.ch>
parent 764797fe
...@@ -56,8 +56,8 @@ class GenerateQuartusProject(Action): ...@@ -56,8 +56,8 @@ class GenerateQuartusProject(Action):
top_mod.syn_grade, top_mod.syn_grade,
top_mod.syn_package, top_mod.syn_package,
top_mod.syn_top) top_mod.syn_top)
prj.preflow = None prj.preflow = top_mod.quartus_preflow
prj.postflow = None prj.postflow = top_mod.quartus_postflow
prj.emit() prj.emit()
...@@ -68,7 +68,7 @@ class GenerateQuartusProject(Action): ...@@ -68,7 +68,7 @@ class GenerateQuartusProject(Action):
fileset.add(non_dependable) fileset.add(non_dependable)
prj = QuartusProject(top_mod.syn_project) prj = QuartusProject(top_mod.syn_project)
prj.read() prj.read()
prj.preflow = None prj.preflow = top_mod.quartus_preflow
prj.postflow = None prj.postflow = top_mod.quartus_postflow
prj.add_files(fileset) prj.add_files(fileset)
prj.emit() prj.emit()
...@@ -70,6 +70,10 @@ class ManifestParser(ConfigParser): ...@@ -70,6 +70,10 @@ class ManifestParser(ConfigParser):
self.add_option('force_tool', default=None, help="Force certain version of a tool, e.g. 'ise < 13.2' or 'iverilog == 0.9.6", self.add_option('force_tool', default=None, help="Force certain version of a tool, e.g. 'ise < 13.2' or 'iverilog == 0.9.6",
type='') type='')
self.add_delimiter()
self.add_option('quartus_preflow', default=None, help = "Quartus pre-flow script file", type = '')
self.add_option('quartus_postflow', default=None, help = "Quartus post-flow script file", type = '')
self.add_delimiter() self.add_delimiter()
self.add_option('include_dirs', default=None, help="Include dirs for Verilog sources", type=[]) self.add_option('include_dirs', default=None, help="Include dirs for Verilog sources", type=[])
self.add_type('include_dirs', type="") self.add_type('include_dirs', type="")
......
...@@ -75,6 +75,8 @@ class Module(object): ...@@ -75,6 +75,8 @@ class Module(object):
self.vlog_opt = None self.vlog_opt = None
self.vcom_opt = None self.vcom_opt = None
self.revision = None self.revision = None
self.quartus_preflow = None
self.quartus_postflow = None
self._files = None self._files = None
self.manifest = None self.manifest = None
self.incl_makefiles = [] self.incl_makefiles = []
...@@ -224,7 +226,7 @@ class Module(object): ...@@ -224,7 +226,7 @@ class Module(object):
self.manifest_dict = opt_map self.manifest_dict = opt_map
def process_manifest(self): def process_manifest(self):
from srcfile import VerilogFile, VHDLFile, SourceFileSet from srcfile import TCLFile, VerilogFile, VHDLFile, SourceFileSet
if self.isprocessed is True: if self.isprocessed is True:
return return
if self.manifest_dict is None: if self.manifest_dict is None:
...@@ -393,6 +395,22 @@ class Module(object): ...@@ -393,6 +395,22 @@ class Module(object):
self.syn_project = self.manifest_dict["syn_project"] self.syn_project = self.manifest_dict["syn_project"]
self.syn_top = self.manifest_dict["syn_top"] self.syn_top = self.manifest_dict["syn_top"]
if self.manifest_dict["quartus_preflow"] != None:
path = path_mod.rel2abs(self.manifest_dict["quartus_preflow"], self.path);
if not os.path.exists(path):
p.error("quartus_preflow file listed in " + self.manifest.path + " doesn't exist: "
+ path + ".\nExiting.")
quit()
self.quartus_preflow = TCLFile(path)
if self.manifest_dict["quartus_postflow"] != None:
path = path_mod.rel2abs(self.manifest_dict["quartus_postflow"], self.path);
if not os.path.exists(path):
p.error("quartus_postflow file listed in " + self.manifest.path + " doesn't exist: "
+ path + ".\nExiting.")
quit()
self.quartus_postflow = TCLFile(path)
self.isparsed = True self.isparsed = True
self.isprocessed = True self.isprocessed = True
......
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