Fix and document Xilinx Vivado and PlanAhead project language selection

parent 530d2f14
......@@ -1117,6 +1117,8 @@ This project makes use of **custom Xilinx Vivado properties** and **custom Pytho
modules = { "local" : [ "../../../../top/afc_v3/vivado/dbe_bpm2" ] };
.. note:: If you are generating HDL code from a Xilinx IP library, you may need to select the target language by setting the ``language`` top manifest variable to either ``vhdl`` or ``verilog``. If the ``language`` variable is not defined, ``hdlmake`` will choose ``vhdl`` as the default HDL language.
Intel Quartus
~~~~~~~~~~~~~
......@@ -1402,6 +1404,8 @@ Top Manifest variables
+----------------+--------------+-----------------------------------------------------------------+-----------+
| incl_makefiles | list, str | List of .mk files appended to toplevel makefile | [] |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| language | str | Select the default HDL language if required (verilog, vhdl) | "vhdl" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
Universal variables
......
......@@ -84,6 +84,8 @@ $(TCL_CLOSE)'''
"""Create the property list"""
syn_properties = self.manifest_dict.get("syn_properties")
language = self.manifest_dict.get("language")
if language == None:
language = "vhdl"
properties = [
['part', '$(SYN_DEVICE)' +
'$(SYN_PACKAGE)' +
......
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