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Hdlmake
Commits
b2341837
Commit
b2341837
authored
Aug 10, 2016
by
Javier D. Garcia-Lasheras
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Plain Diff
Vivado, IVerilog and GHDL classes share common code now
parent
a90100a1
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4 changed files
with
30 additions
and
12 deletions
+30
-12
ghdl.py
hdlmake/tools/ghdl.py
+7
-2
iverilog.py
hdlmake/tools/iverilog.py
+10
-4
make_sim.py
hdlmake/tools/make_sim.py
+9
-4
vivado.py
hdlmake/tools/vivado.py
+4
-2
No files found.
hdlmake/tools/ghdl.py
View file @
b2341837
...
...
@@ -46,11 +46,16 @@ class ToolGHDL(ToolSim):
CLEAN_TARGETS
=
{
'clean'
:
[
"*.cf"
,
"*.o"
,
"$(TOP_MODULE)"
,
"work"
],
'mrproper'
:
[
"*.vcd"
]}
SIMULATOR_CONTROLS
=
{
'vlog'
:
None
,
'vhdl'
:
'ghdl -a $<'
,
'compiler'
:
'ghdl -e $(TOP_MODULE)'
}
def
__init__
(
self
):
super
(
ToolGHDL
,
self
)
.
__init__
()
self
.
_tool_info
.
update
(
ToolGHDL
.
TOOL_INFO
)
self
.
_hdl_files
.
extend
(
ToolGHDL
.
HDL_FILES
)
self
.
_clean_targets
.
update
(
ToolGHDL
.
CLEAN_TARGETS
)
self
.
_simulator_controls
.
update
(
ToolGHDL
.
SIMULATOR_CONTROLS
)
def
makefile_sim_options
(
self
):
"""Print the GHDL options to the Makefile"""
...
...
@@ -66,7 +71,7 @@ class ToolGHDL(ToolSim):
def
makefile_sim_compilation
(
self
):
"""Print the GDHL simulation compilation target"""
self
.
writeln
(
"simulation: $(VERILOG_OBJ) $(VHDL_OBJ)"
)
self
.
writeln
(
"
\t\t
ghdl -e $(TOP_MODULE)"
)
self
.
writeln
(
"
\t\t
"
+
self
.
_simulator_controls
[
'compiler'
]
)
self
.
writeln
(
'
\n
'
)
self
.
makefile_sim_dep_files
(
"ghdl -a $<"
)
self
.
makefile_sim_dep_files
()
hdlmake/tools/iverilog.py
View file @
b2341837
...
...
@@ -46,17 +46,24 @@ class ToolIVerilog(ToolSim):
CLEAN_TARGETS
=
{
'clean'
:
[
"run.command"
,
"ivl_vhdl_work"
,
"work"
],
'mrproper'
:
[
"*.vcd"
,
"*.vvp"
]}
SIMULATOR_CONTROLS
=
{
'vlog'
:
'echo $< >> run.command'
,
'vhdl'
:
'echo $< >> run.command'
,
'compiler'
:
'iverilog $(IVERILOG_OPT) '
'-s $(TOP_MODULE) '
'-o $(TOP_MODULE).vvp '
'-c run.command'
}
def
__init__
(
self
):
super
(
ToolIVerilog
,
self
)
.
__init__
()
self
.
_tool_info
.
update
(
ToolIVerilog
.
TOOL_INFO
)
self
.
_hdl_files
.
extend
(
ToolIVerilog
.
HDL_FILES
)
self
.
_clean_targets
.
update
(
ToolIVerilog
.
CLEAN_TARGETS
)
self
.
_simulator_controls
.
update
(
ToolIVerilog
.
SIMULATOR_CONTROLS
)
def
makefile_sim_compilation
(
self
):
"""Generate compile simulation Makefile target for IVerilog"""
self
.
writeln
(
"simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)"
)
self
.
writeln
(
"
\t\t
iverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command"
)
self
.
writeln
(
"
\t\t
"
+
self
.
_simulator_controls
[
'compiler'
])
self
.
writeln
()
self
.
writeln
(
"include_dirs:"
)
self
.
writeln
(
"
\t\t
echo
\"
# IVerilog command file,"
...
...
@@ -66,8 +73,7 @@ class ToolIVerilog(ToolSim):
for
inc
in
top_module
.
get_include_dirs_list
():
self
.
writeln
(
"
\t\t
echo
\"
+incdir+"
+
inc
+
"
\"
>> run.command"
)
self
.
writeln
(
'
\n
'
)
compilation_command
=
"echo $< >> run.command"
self
.
makefile_sim_dep_files
(
compilation_command
)
self
.
makefile_sim_dep_files
()
def
makefile_sim_options
(
self
):
"""Print the IVerilog options to the Makefile"""
...
...
hdlmake/tools/make_sim.py
View file @
b2341837
...
...
@@ -5,7 +5,7 @@ import string
from
.makefile
import
ToolMakefile
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
class
ToolSim
(
ToolMakefile
):
...
...
@@ -13,6 +13,7 @@ class ToolSim(ToolMakefile):
def
__init__
(
self
):
super
(
ToolSim
,
self
)
.
__init__
()
self
.
_simulator_controls
=
{}
def
makefile_sim_top
(
self
):
"""Generic method to write the simulation Makefile top section"""
...
...
@@ -34,7 +35,6 @@ PWD := $$(shell pwd)
def
makefile_sim_sources
(
self
):
"""Generic method to write the simulation Makefile HDL sources"""
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
fileset
=
self
.
fileset
self
.
write
(
"VERILOG_SRC := "
)
for
vlog
in
fileset
.
filter
(
VerilogFile
):
...
...
@@ -77,7 +77,7 @@ PWD := $$(shell pwd)
"
\\
"
)
self
.
writeln
()
def
makefile_sim_dep_files
(
self
,
compilation_command
):
def
makefile_sim_dep_files
(
self
):
"""Print dummy targets to handle file dependencies"""
fileset
=
self
.
fileset
for
file_aux
in
fileset
:
...
...
@@ -100,7 +100,12 @@ PWD := $$(shell pwd)
# the file is included -> we depend directly on it
self
.
write
(
"
\\\n
"
+
dep_file
.
rel_path
())
self
.
writeln
()
self
.
writeln
(
"
\t\t
"
+
compilation_command
)
if
isinstance
(
file_aux
,
VHDLFile
):
command_key
=
'vhdl'
elif
(
isinstance
(
file_aux
,
VerilogFile
)
or
isinstance
(
file_aux
,
SVFile
)):
command_key
=
'vlog'
self
.
writeln
(
"
\t\t
"
+
self
.
_simulator_controls
[
command_key
])
self
.
write
(
"
\t\t
@"
+
path_mod
.
mkdir_command
()
+
" $(dir $@)"
)
self
.
writeln
(
" && touch $@
\n
"
)
self
.
writeln
()
...
...
hdlmake/tools/vivado.py
View file @
b2341837
...
...
@@ -57,7 +57,8 @@ class ToolVivado(ToolXilinx, ToolSim):
SIMULATOR_CONTROLS
=
{
'vlog'
:
'xvlog $<'
,
'vhdl'
:
'xvhdl $<'
,
'compiler'
:
'xelab $(TOP_MODULE) -s $(TOP_MODULE)'
}
'compiler'
:
'xelab -debug all $(TOP_MODULE) '
'-s $(TOP_MODULE)'
}
def
__init__
(
self
):
super
(
ToolVivado
,
self
)
.
__init__
()
...
...
@@ -65,6 +66,7 @@ class ToolVivado(ToolXilinx, ToolSim):
self
.
_supported_files
.
extend
(
ToolVivado
.
SUPPORTED_FILES
)
self
.
_clean_targets
.
update
(
ToolVivado
.
CLEAN_TARGETS
)
self
.
_tcl_controls
.
update
(
ToolVivado
.
TCL_CONTROLS
)
self
.
_simulator_controls
.
update
(
ToolVivado
.
SIMULATOR_CONTROLS
)
def
makefile_sim_compilation
(
self
):
...
...
@@ -72,6 +74,6 @@ class ToolVivado(ToolXilinx, ToolSim):
self
.
writeln
(
"simulation: $(VERILOG_OBJ) $(VHDL_OBJ)"
)
self
.
writeln
(
"
\t\t
"
+
ToolVivado
.
SIMULATOR_CONTROLS
[
'compiler'
])
self
.
writeln
()
self
.
makefile_sim_dep_files
(
ToolVivado
.
SIMULATOR_CONTROLS
[
'vhdl'
]
)
self
.
makefile_sim_dep_files
()
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