Code refactored with autopep8

parent 4e3713cc
......@@ -122,7 +122,7 @@ def _action_runner(modules_pool):
modules_pool.simulation_makefile()
elif top_mod.action == "synthesis":
modules_pool.synthesis_project()
#modules_pool.synthesis_makefile()
# modules_pool.synthesis_makefile()
elif top_mod.action == "qsys_hw_tcl_update":
if not top_mod.manifest_dict["hw_tcl_filename"]:
logging.error("'hw_tcl_filename' manifest variable has to be specified. "
......
......@@ -30,4 +30,3 @@ from .tree import ActionTree
from .synthesis import ActionSynthesis
from .simulation import ActionSimulation
from .qsys_hw_tcl_update import QsysHwTclUpdate
......@@ -33,9 +33,10 @@ from hdlmake.tools import (
ToolIVerilog, ToolISim, ToolModelsim,
ToolActiveHDL, ToolRiviera, ToolGHDL)
class ActionSimulation(
ToolIVerilog, ToolISim, ToolModelsim,
ToolActiveHDL, ToolRiviera, ToolGHDL):
ToolActiveHDL, ToolRiviera, ToolGHDL):
"""This class contains the simulation specific methods"""
......
......@@ -92,4 +92,3 @@ class ToolDiamond(ToolSyn):
self.writeln(hdl.format('add', file_aux.rel_path()))
self.writeln("endef")
self.writeln("export TCL_FILES")
......@@ -139,4 +139,3 @@ class ToolISE(ToolSyn):
self.writeln("project set top $(TOP_MODULE)")
self.writeln("endef")
self.writeln("export TCL_FILES")
......@@ -252,4 +252,3 @@ fuse:
self.write(" \\\n" + os.path.join(dep_file.rel_path()))
self.write('\n')
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@\n")
......@@ -80,9 +80,9 @@ class ToolLibero(ToolSyn):
syn_package = top_module.manifest_dict["syn_package"]
create_tmp = self._tcl_controls["create"]
self._tcl_controls["create"] = create_tmp.format(syn_project,
syn_device.upper(),
syn_package.upper(),
syn_grade)
syn_device.upper(),
syn_package.upper(),
syn_grade)
super(ToolLibero, self).makefile_syn_tcl(top_module)
def makefile_syn_files(self, fileset):
......@@ -131,4 +131,3 @@ class ToolLibero(ToolSyn):
ret.append("endef")
ret.append("export TCL_FILES")
self.writeln('\n'.join(ret))
......@@ -103,4 +103,3 @@ sim_post_cmd:
"""Print simulation PHONY target list to the Makefile"""
self.writeln(
".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation")
......@@ -5,6 +5,7 @@ import string
from .makefile import ToolMakefile
from hdlmake.util import path as path_mod
class ToolSyn(ToolMakefile):
"""Class that provides the synthesis Makefile writing methods and status"""
......@@ -215,13 +216,12 @@ syn_post_bitstream_cmd:
"""Print the Makefile clean target for synthesis"""
self.makefile_clean()
self.writeln("\t\t" + path_mod.del_command() +
" synthesize translate map par bitstream")
" synthesize translate map par bitstream")
self.writeln("\t\t" + path_mod.del_command() +
" tcl_synthesize tcl_translate tcl_map tcl_par tcl_bitstream")
" tcl_synthesize tcl_translate tcl_map tcl_par tcl_bitstream")
self.makefile_mrproper()
def makefile_syn_phony(self):
"""Print synthesis PHONY target list to the Makefile"""
self.writeln(
".PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis")
......@@ -28,6 +28,7 @@ import os
from hdlmake.util import path as path_mod
from hdlmake.action import Action
class ToolMakefile(Action):
"""Class that provides the Makefile writing methods and status"""
......
......@@ -56,4 +56,3 @@ class ToolPlanAhead(ToolXilinx):
self._supported_files.extend(ToolPlanAhead.SUPPORTED_FILES)
self._clean_targets.update(ToolPlanAhead.CLEAN_TARGETS)
self._tcl_controls.update(ToolPlanAhead.TCL_CONTROLS)
......@@ -82,7 +82,6 @@ class ToolQuartus(ToolSyn):
"set_location_assignment": SET_LOCATION_ASSIGNMENT,
"set_global_assignment": SET_GLOBAL_ASSIGNMENT}
def __init__(self):
super(ToolQuartus, self).__init__()
self._tool_info.update(ToolQuartus.TOOL_INFO)
......@@ -94,6 +93,7 @@ class ToolQuartus(ToolSyn):
def makefile_syn_tcl(self, top_module):
"""Add initial properties to the Altera Quartus project"""
import re
def _emit_property(command, what=None, name=None, name_type=None,
from_=None, to_=None, section_id=None):
"""Emit a formated property for Altera Quartus TCL"""
......@@ -116,6 +116,7 @@ class ToolQuartus(ToolSyn):
words.append("-section_id")
words.append(section_id)
return ' '.join(words)
def __get_family_string(family=None, device=None):
"""Function that looks for a existing device family name and
try to guess the value from the device string if not defined"""
......@@ -137,6 +138,7 @@ class ToolQuartus(ToolSyn):
"specify in Manifest.py using syn_family!")
sys.exit("\nExiting")
return family
# Set the core Quartus project properties
family_string = __get_family_string(
family=top_module.manifest_dict["syn_family"],
......@@ -148,14 +150,14 @@ class ToolQuartus(ToolSyn):
command_list = []
command_list.append(self._tcl_controls["create"])
command_list.append(_emit_property(self.SET_GLOBAL_ASSIGNMENT,
name_type='FAMILY',
name='"' + family_string + '"'))
name_type='FAMILY',
name='"' + family_string + '"'))
command_list.append(_emit_property(self.SET_GLOBAL_ASSIGNMENT,
name_type='DEVICE',
name=device_string))
name_type='DEVICE',
name=device_string))
command_list.append(_emit_property(self.SET_GLOBAL_ASSIGNMENT,
name_type='TOP_LEVEL_ENTITY',
name=top_module.manifest_dict["syn_top"]))
name_type='TOP_LEVEL_ENTITY',
name=top_module.manifest_dict["syn_top"]))
# Insert the Quartus standard control TCL files
if top_module.manifest_dict["quartus_preflow"] is not None:
path = path_mod.compose(
......@@ -196,7 +198,6 @@ class ToolQuartus(ToolSyn):
self._tcl_controls["create"] = '\n'.join(command_list)
super(ToolQuartus, self).makefile_syn_tcl(top_module)
def makefile_syn_files(self, fileset):
"""Write the files TCL section of the Makefile"""
self.writeln("define TCL_FILES")
......@@ -241,4 +242,3 @@ class ToolQuartus(ToolSyn):
self.writeln('\n'.join(ret))
self.writeln("endef")
self.writeln("export TCL_FILES")
......@@ -80,4 +80,3 @@ class ToolRiviera(VsimMakefileWriter):
self.vcom_flags.append("-2008")
self._tool_info.update(ToolRiviera.TOOL_INFO)
self._clean_targets.update(ToolRiviera.CLEAN_TARGETS)
......@@ -96,7 +96,7 @@ class VsimMakefileWriter(ToolSim):
\t\t%s $< . 2>&1
""" % (name, src, path_mod.copy_command())
return rule
#self.writeln("INCLUDE_DIRS := +incdir+%s" %
# self.writeln("INCLUDE_DIRS := +incdir+%s" %
# ('+'.join(top_module.include_dirs)))
libs = set(f.library for f in fileset)
self.write('LIBS := ')
......@@ -123,7 +123,7 @@ class VsimMakefileWriter(ToolSim):
self.write(lib + path_mod.slash_char() + "." + lib + ":\n")
vmap_command = "vmap $(VMAP_FLAGS)"
self.write(' '.join(["\t(vlib", lib, "&&", vmap_command, lib, "&&",
"touch", lib + path_mod.slash_char() + "." + lib, ")"]))
"touch", lib + path_mod.slash_char() + "." + lib, ")"]))
self.write(' '.join(["||", path_mod.del_command(), lib, "\n"]))
self.write('\n\n')
# rules for all _primary.dat files for sv
......@@ -185,4 +185,3 @@ class VsimMakefileWriter(ToolSim):
vhdl.vcom_opt, "-work", lib, "$< "]))
self.writeln("\t\t@" + path_mod.mkdir_command() +
" $(dir $@) && touch $@ \n\n")
......@@ -61,4 +61,3 @@ class ToolVivado(ToolXilinx):
self._supported_files.extend(ToolVivado.SUPPORTED_FILES)
self._clean_targets.update(ToolVivado.CLEAN_TARGETS)
self._tcl_controls.update(ToolVivado.TCL_CONTROLS)
......@@ -53,7 +53,6 @@ class ToolXilinx(ToolSyn):
'wait_on_run impl_1',
'install_source': '$(PROJECT).runs/impl_1/$(SYN_TOP).bit'}
def __init__(self):
super(ToolXilinx, self).__init__()
self._hdl_files.extend(ToolXilinx.HDL_FILES)
......@@ -93,5 +92,3 @@ class ToolXilinx(ToolSyn):
self.writeln('update_compile_order -fileset sim_1')
self.writeln("endef")
self.writeln("export TCL_FILES")
......@@ -168,6 +168,7 @@ def check_windows():
else:
return False
def del_command():
"""Get a string with the O.S. specific delete command"""
if check_windows():
......@@ -175,6 +176,7 @@ def del_command():
else:
return "rm -rf"
def copy_command():
"""Get a string with the O.S. specific copy command"""
if check_windows():
......@@ -182,6 +184,7 @@ def copy_command():
else:
return "cp"
def mkdir_command():
"""Get a string with the O.S. specific mkdir command"""
if check_windows():
......@@ -189,11 +192,10 @@ def mkdir_command():
else:
return "mkdir -p"
def slash_char():
"""Get a string with the O.S. specific path separator"""
if check_windows():
return "\\"
else:
return "/"
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