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Hdlmake
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c86ec698
Commit
c86ec698
authored
Mar 28, 2015
by
Javier D. Garcia-Lasheras
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Merge remote-tracking branch 'origin/VHDL_parser_fix' into release-2.1
parents
66d11884
187e97e8
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117 additions
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170 deletions
+117
-170
vhdl_parser.py
hdlmake/vhdl_parser.py
+74
-131
Makefile
tests/questa_uvm_sv/sim/tests/Makefile
+43
-39
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hdlmake/vhdl_parser.py
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tests/questa_uvm_sv/sim/tests/Makefile
View file @
c86ec698
...
...
@@ -6,65 +6,79 @@
## variables #############################
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
/opt/questa_sv_afv_10.
3c_1
/questasim//bin/..
MODELSIM_INI_PATH
:=
/opt/questa_sv_afv_10.
4
/questasim//bin/..
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VERILOG_SRC
:=
src/genericTest.sv
\
../../rtl/RTLTopModuleVerilogSimulationModel.vo
\
VERILOG_SRC
:=
../../ipcores/ipcore/ipcore.sv
\
../../rtl/RTL_SVPackage.sv
\
../../rtl/RTLTopModuleSV.sv
\
src/genericTest.sv
\
../../rtl/RTLTopModuleVerilogSimulationModel.vo
\
../../rtl/include/includeModuleSV.sv
\
../../
ipcores/ipcore/ipcore
.sv
\
../../
rtl/RTLTopModuleSV
.sv
\
VERILOG_OBJ
:=
work/genericTest/.genericTest_sv
\
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo
\
VERILOG_OBJ
:=
work/ipcore/.ipcore_sv
\
work/RTL_SVPackage/.RTL_SVPackage_sv
\
work/RTLTopModuleSV/.RTLTopModuleSV_sv
\
work/genericTest/.genericTest_sv
\
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo
\
work/includeModuleSV/.includeModuleSV_sv
\
work/
ipcore/.ipcore
_sv
\
work/
RTLTopModuleSV/.RTLTopModuleSV
_sv
\
VHDL_SRC
:=
../../rtl/include/includeModuleVHDL.vhdl
\
VHDL_SRC
:=
../../rtl/include/includeModuleBVHDL.vhdl
\
../../rtl/include/includeModuleVHDL.vhdl
\
../../rtl/include/includeModuleAVHDL.vhdl
\
../../rtl/include/includeModuleBVHDL.vhdl
\
../../rtl/RTLTopModuleVHDL.vhdl
\
VHDL_OBJ
:=
work/includeModuleVHDL/.includeModuleVHDL_vhdl
\
VHDL_OBJ
:=
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl
\
work/includeModuleVHDL/.includeModuleVHDL_vhdl
\
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl
\
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl
\
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl
\
LIBS
:=
work
LIB_IND
:=
work/.work
## rules #################################
sim
:
sim_pre_cmd modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
local
:
sim_pre_cmd simulation sim_post_cmd
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
sim_pre_cmd
:
sim_post_cmd
:
sim
sim_post_cmd
:
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
clean
:
rm
-rf
./modelsim.ini
$(LIBS)
transcript
*
.vcd
*
.wlf
.PHONY
:
clean sim_pre_cmd sim_post_cmd
.PHONY
:
clean sim_pre_cmd sim_post_cmd
simulation
work/.work
:
(
vlib work
&&
vmap
-modelsimini
modelsim.ini work
&&
touch
work/.work
)||
rm
-rf
work
work/ipcore/.ipcore_sv
:
../../ipcores/ipcore/ipcore.sv
\
../../ipcores/ipcore/include/ipcoreInclude.sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
+incdir+../../ipcores/ipcore/include+../../ipcores/ipcore
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/RTL_SVPackage/.RTL_SVPackage_sv
:
../../rtl/RTL_SVPackage.sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
+incdir+../../rtl/include+../../rtl
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/genericTest/.genericTest_sv
:
src/genericTest.sv
\
../environment/env.sv
\
../sequences/sequence.sv
\
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo
\
../environment/Env_pkg.sv
\
src/FullTest_pkg.sv
\
../environment/top.sv
\
work/RTLTopModuleSV/.RTLTopModuleSV_sv
\
../sequences/sequence.sv
../environment/top.sv
\
../environment/Env_pkg.sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
+incdir+../environment+../sequences+src +incdir+../../mvc//questa_mvc_src/sv+../../mvc/questa_mvc_src/sv/mvc_base+../../mvc/include+../../uvm-1.1d/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
...
...
@@ -74,49 +88,39 @@ work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo:
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/RTL_SVPackage/.RTL_SVPackage_sv
:
../../rtl/RTL_SVPackage.sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
+incdir+../../rtl/include+../../rtl
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/RTLTopModuleSV/.RTLTopModuleSV_sv
:
../../rtl/RTLTopModuleSV.sv
\
work/RTL_SVPackage/.RTL_SVPackage_sv
\
work/ipcore/.ipcore_sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
+incdir+../../rtl/include+../../rtl
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/includeModuleSV/.includeModuleSV_sv
:
../../rtl/include/includeModuleSV.sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
+incdir+../../rtl/include+../../rtl/include
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/ipcore/.ipcore_sv
:
../../ipcores/ipcore/ipcore.sv
\
../../ipcores/ipcore/include/ipcoreInclude.sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
+incdir+../../ipcores/ipcore/include+../../ipcores/ipcore
$<
work/RTLTopModuleSV/.RTLTopModuleSV_sv
:
../../rtl/RTLTopModuleSV.sv
\
work/ipcore/.ipcore_sv
\
work/includeModuleSV/.includeModuleSV_sv
\
work/RTL_SVPackage/.RTL_SVPackage_sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
+incdir+../../rtl/include+../../rtl
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/includeModule
VHDL/.includeModuleVHDL_vhdl
:
../../rtl/include/includeModule
VHDL.vhdl
work/includeModule
BVHDL/.includeModuleBVHDL_vhdl
:
../../rtl/include/includeModuleB
VHDL.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/includeModule
AVHDL/.includeModuleAVHDL_vhdl
:
../../rtl/include/includeModuleA
VHDL.vhdl
work/includeModule
VHDL/.includeModuleVHDL_vhdl
:
../../rtl/include/includeModule
VHDL.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/includeModule
BVHDL/.includeModuleBVHDL_vhdl
:
../../rtl/include/includeModuleB
VHDL.vhdl
work/includeModule
AVHDL/.includeModuleAVHDL_vhdl
:
../../rtl/include/includeModuleA
VHDL.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl
:
../../rtl/RTLTopModuleVHDL.vhdl
\
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl
\
work/includeModuleVHDL/.includeModuleVHDL_vhdl
\
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl
\
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
...
...
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