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c97cff89
Commit
c97cff89
authored
Mar 30, 2019
by
Javier D. Garcia-Lasheras
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Fix and upgrade the counter test demo HDL files
parent
1627ac83
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4 changed files
with
39 additions
and
33 deletions
+39
-33
counter.v
tests/counter/modules/counter/verilog/counter.v
+16
-12
counter.vhd
tests/counter/modules/counter/vhdl/counter.vhd
+12
-12
counter_tb.v
tests/counter/testbench/counter_tb/verilog/counter_tb.v
+3
-4
counter_tb.vhd
tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd
+8
-5
No files found.
tests/counter/modules/counter/verilog/counter.v
View file @
c97cff89
...
...
@@ -20,28 +20,32 @@ module counter (
input
clock
,
clear
,
count
;
//--------- Internal Variables ------------------------
reg
ready
=
0
;
reg
[
23
:
0
]
divider
;
reg
[
7
:
0
]
Q
;
//--------- Code Starts Here --------------------------
always
@
(
posedge
clock
)
begin
if
(
ready
)
if
(
clear
)
begin
if
(
divider
==
cycles_per_second
)
begin
divider
<=
0
;
Q
<=
{
Q
[
6
:
0
]
,
Q
[
7
]
};
end
else
divider
<=
divider
+
1
;
Q
<=
0
;
divider
<=
0
;
end
else
begin
ready
<=
1
;
Q
<=
8'b00010001
;
divider
<=
0
;
if
(
count
)
begin
if
(
divider
==
cycles_per_second
)
begin
divider
<=
0
;
Q
<=
Q
+
1
;
end
else
begin
divider
<=
divider
+
1
;
Q
<=
Q
;
end
end
end
end
...
...
tests/counter/modules/counter/vhdl/counter.vhd
View file @
c97cff89
...
...
@@ -24,7 +24,6 @@ end counter;
-------------------------------------------------------
architecture
behv
of
counter
is
signal
ready
:
std_logic
;
signal
Pre_Q
:
unsigned
(
7
downto
0
);
signal
divider
:
unsigned
(
23
downto
0
);
...
...
@@ -33,18 +32,19 @@ begin
process
(
clock
,
count
,
clear
)
begin
if
(
clock
=
'1'
and
clock
'event
)
then
if
ready
=
'1'
then
if
divider
=
cycles_per_second
then
divider
<=
(
others
=>
'0'
);
Pre_Q
(
7
downto
1
)
<=
Pre_Q
(
6
downto
0
);
Pre_Q
(
0
)
<=
Pre_Q
(
7
);
else
divider
<=
divider
+
1
;
end
if
;
else
ready
<=
'1'
;
Pre_Q
<=
"00010001"
;
if
clear
=
'1'
then
Pre_Q
<=
(
others
=>
'0'
);
divider
<=
(
others
=>
'0'
);
else
if
count
=
'1'
then
if
divider
=
cycles_per_second
then
divider
<=
(
others
=>
'0'
);
Pre_Q
<=
Pre_Q
+
1
;
else
divider
<=
divider
+
1
;
Pre_Q
<=
Pre_Q
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
...
...
tests/counter/testbench/counter_tb/verilog/counter_tb.v
View file @
c97cff89
...
...
@@ -8,7 +8,7 @@ module counter_tb();
reg
clock
,
clear
,
count
;
wire
[
7
:
0
]
Q
;
defparam
U_counter
.
cycles_per_second
=
50
0
;
defparam
U_counter
.
cycles_per_second
=
1
0
;
// Initialize all variables
initial
begin
...
...
@@ -22,9 +22,8 @@ initial begin
count
=
0
;
// initial value of count enable
#
5
clear
=
1
;
// Assert the clear signal
#
10
clear
=
0
;
// De-assert clear signal
#
10
count
=
1
;
// Start count
#
10000
count
=
0
;
// De-assert count enable
#
5
$
finish
;
// Terminate simulation
#
40
count
=
1
;
// Start count
#
1000
$
finish
;
// Terminate simulation
end
// Clock generator
...
...
tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd
View file @
c97cff89
...
...
@@ -33,7 +33,7 @@ architecture testbench of counter_tb is
begin
U_counter
:
counter
generic
map
(
cycles_per_second
=>
50
0
)
generic
map
(
cycles_per_second
=>
1
0
)
port
map
(
t_clock
,
t_clear
,
t_count
,
t_Q
);
process
...
...
@@ -47,12 +47,15 @@ begin
process
begin
t_clear
<=
'1'
;
--
start counting
t_count
<=
'
1
'
;
t_clear
<=
'1'
;
--
clear counter
t_count
<=
'
0
'
;
wait
for
50
ns
;
t_clear
<=
'0'
;
-- clear output
wait
for
1000
ns
;
t_clear
<=
'0'
;
-- release clear
wait
for
200
ns
;
t_count
<=
'1'
;
wait
for
1000
ns
;
-- start counting
report
"Testbench of Adder completed successfully!"
severity
note
;
...
...
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