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Hdlmake
Commit cdfa04b3 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Fix error when locating Verilog and SystemVerilog includes

parent b2341837
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Showing with 17 additions and 7 deletions
hdlmake/module/core.py
View file @ cdfa04b3
......@@ -144,6 +144,11 @@ class ModuleCore(ModuleConfig):
"""
from hdlmake.srcfile import create_source_file, SourceFileSet
srcs = SourceFileSet()
# Check if this is the top module and grab the include_dirs
if self.parent is None:
include_dirs = self.manifest_dict['include_dirs']
else:
include_dirs = self.top_module.manifest_dict['include_dirs']
for path_aux in paths:
if os.path.isdir(path_aux):
dir_ = os.listdir(path_aux)
......@@ -152,9 +157,11 @@ class ModuleCore(ModuleConfig):
if not os.path.isdir(f_dir):
srcs.add(create_source_file(path=f_dir,
module=self,
library=self.library))
library=self.library,
include_dirs=include_dirs))
else:
srcs.add(create_source_file(path=path_aux,
module=self,
library=self.library))
library=self.library,
include_dirs=include_dirs))
return srcs
hdlmake/module/module.py
View file @ cdfa04b3
......@@ -119,13 +119,16 @@ class Module(ModuleContent):
self._set_simulation_options()
def _set_simulation_options(self):
"""This set the simulation option for all the files in the Module"""
from hdlmake.srcfile import VerilogFile, VHDLFile
"""This set the simulation option for all the files in the Module."""
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
include_dirs_list = self.get_include_dirs_list()
for file_aux in self.files:
if isinstance(file_aux, VerilogFile):
file_aux.vsim_opt = self.manifest_dict["vsim_opt"]
file_aux.include_dirs = include_dirs_list
elif isinstance(file_aux, SVFile):
file_aux.vsim_opt = self.manifest_dict["vsim_opt"]
file_aux.include_dirs = include_dirs_list
elif isinstance(file_aux, VHDLFile):
file_aux.vcom_opt = self.manifest_dict["vcom_opt"]
......@@ -139,7 +142,7 @@ class Module(ModuleContent):
self.path, self.manifest_dict["include_dirs"])
include_dirs.append(dir_list)
else:
dir_list = [path_mod.compose(self.path, x) for
dir_list = [path_mod.compose(x, self.path) for
x in self.manifest_dict["include_dirs"]]
include_dirs.extend(dir_list)
# Analyze included dirs and report if any issue is found
......
hdlmake/vlog_parser.py
View file @ cdfa04b3
......@@ -112,13 +112,13 @@ class VerilogPreprocessor(object):
possible_file = os.path.join(parent_dir, filename)
if os.path.isfile(possible_file):
return os.path.abspath(possible_file)
for searchdir in self.vpp_searchdir:
for searchdir in self.vlog_file.include_dirs:
probable_file = os.path.join(searchdir, filename)
if os.path.isfile(probable_file):
return os.path.abspath(probable_file)
logging.error("Can't find %s for %s in any of the include "
"directories: %s", filename, self.vlog_file.file_path,
', '.join(self.vpp_searchdir))
', '.join(self.vlog_file.include_dirs))
sys.exit("\nExiting")
def _parse_macro_def(self, macro):
......
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