Commit d0d037d3 authored by Joshua A. Einstein-Curtis's avatar Joshua A. Einstein-Curtis Committed by Javier D. Garcia-Lasheras

SystemVerilog and Verilog file descriptions looked to be flipped in quartus.py

parent 2712f107
......@@ -68,9 +68,9 @@ class ToolQuartus(ToolSyn):
HDL_FILES = {
VHDLFile: _QUARTUS_SOURCE.format('VHDL_FILE') +
_QUARTUS_LIBRARY,
VerilogFile: _QUARTUS_SOURCE.format('SYSTEMVERILOG_FILE') +
VerilogFile: _QUARTUS_SOURCE.format('VERILOG_FILE') +
_QUARTUS_LIBRARY,
SVFile: _QUARTUS_SOURCE.format('VERILOG_FILE') +
SVFile: _QUARTUS_SOURCE.format('SYSTEMVERILOG_FILE') +
_QUARTUS_LIBRARY}
CLEAN_TARGETS = {'clean': ["*.rpt", "*.smsg", "*.summary",
......
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