Commit d342f521 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras

Merge remote-tracking branch 'origin/release-2.1'

parents aabe6c84 8bd44158
......@@ -46,16 +46,16 @@ master_doc = 'index'
# General information about the project.
project = u'hdlmake'
copyright = u'2014, CERN'
copyright = u'2013-2015, CERN'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# built documents.
#
# The short X.Y version.
version = '2.0'
version = '2.1'
# The full version, including alpha/beta/rc tags.
release = '2.0'
release = '2.1'
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
......
This diff is collapsed.
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -103,9 +103,21 @@ def main():
#
# Load global tool object (global_mod.py)
#
if not top_mod.action:
logging.error("`action' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to handle the project")
quit()
if top_mod.action == "synthesis":
if not top_mod.syn_tool:
logging.error("`syn_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to synthesize the project")
quit()
tool_name = top_mod.syn_tool
elif top_mod.action == "simulation":
if not top_mod.sim_tool:
logging.error("`sim_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to simulate the project")
quit()
tool_name = top_mod.sim_tool
logging.info('import tool module: ' + tool_name)
try:
......@@ -209,7 +221,7 @@ def _get_parser():
"""
usage = """hdlmake [command] [options]"""
description = """Release 2014\n
description = """Version 2.1\n
To see optional arguments for particular command type:
hdlmake <command> --help
\0
......@@ -265,6 +277,9 @@ def _get_parser():
parser.add_argument("--generate-project-vhd", help="generate project.vhd file with a meta package describing the project",
dest="generate_project_vhd", default=False, action="store_true")
parser.add_argument("--force", help="force hdlmake to generate the makefile, even if the specified tool is missing", default=False, action="store_true")
parser.add_argument("--allow-unknown", dest="allow_unknown",
default=False, help="allow unknown option insertions in the child Manifests", action="store_true")
return parser
......
......@@ -49,29 +49,29 @@ class GenerateRemoteSynthesisMakefile(Action):
self._generate_remote_synthesis_makefile(tool_object)
def _search_tcl_file(self, directory=None):
# This function is used in _generate_remote_ise_makefile
if directory is None:
directory = "."
filenames = os.listdir(directory)
tcls = []
for filename in filenames:
file_parts = filename.split('.')
if file_parts[len(file_parts)-1] == "tcl":
tcls.append(filename)
if len(tcls) == 0:
return None
if len(tcls) > 1:
logging.warning("Multiple tcls in the current directory: " + str(tcls) + "\n" +
"Picking the first one: " + tcls[0])
return tcls[0]
def _generate_tcl(self):
# This function is used in _generate_remote_ise_makefile
f = open("run.tcl", "w")
f.write("project open " + self.top_module.syn_project + '\n')
f.write("process run {Generate Programming File} -force rerun_all\n")
f.close()
#def _search_tcl_file(self, directory=None):
# # This function is used in _generate_remote_ise_makefile
# if directory is None:
# directory = "."
# filenames = os.listdir(directory)
# tcls = []
# for filename in filenames:
# file_parts = filename.split('.')
# if file_parts[len(file_parts)-1] == "tcl":
# tcls.append(filename)
# if len(tcls) == 0:
# return None
# if len(tcls) > 1:
# logging.warning("Multiple tcls in the current directory: " + str(tcls) + "\n" +
# "Picking the first one: " + tcls[0])
# return tcls[0]
#def _generate_tcl(self):
# # This function is used in _generate_remote_ise_makefile
# f = open("run.tcl", "w")
# f.write("project open " + self.top_module.syn_project + '\n')
# f.write("process run {Generate Programming File} -force rerun_all\n")
# f.close()
def _generate_remote_synthesis_makefile(self, tool_object):
......@@ -80,14 +80,14 @@ class GenerateRemoteSynthesisMakefile(Action):
top_mod = self.modules_pool.get_top_module()
tcl = self._search_tcl_file()
if tcl is None:
self._generate_tcl()
tcl = "run.tcl"
#tcl = self._search_tcl_file()
#if tcl is None:
# self._generate_tcl()
# tcl = "run.tcl"
files = self.modules_pool.build_global_file_set()
sff = SourceFileFactory()
files.add(sff.new(tcl, module=None))
files.add(sff.new("run.tcl", module=None))
files.add(sff.new(top_mod.syn_project, module=None))
tool_object.generate_remote_synthesis_makefile(files=files, name=top_mod.syn_name,
......
......@@ -148,7 +148,7 @@ end sdb_meta_pkg;""")
env = self.env
if not self.options.force:
if self.env[path_key] is None:
logging.error("Can't generate an " + name + " project. " + name + " not found.")
logging.error("Can't generate the " + name + " project. " + name + " not found.")
quit()
if not env[version_key]:
logging.error(name + " version cannot be deduced. Cannot generate " + name + " "
......
......@@ -207,7 +207,10 @@ class Module(object):
allow_unknown = True
extra_context = {}
else:
allow_unknown = False
if global_mod.options.allow_unknown is True:
allow_unknown = True
else:
allow_unknown = False
extra_context = dict(global_mod.top_module.manifest_dict) # copy the dictionary
del extra_context["modules"]
del extra_context["files"]
......
......@@ -38,11 +38,16 @@ class SourceFile(DepFile):
assert isinstance(path, basestring)
assert isinstance(module, Module)
self.library = library
if not library:
self.library = "work"
DepFile.__init__(self,
file_path=path,
module=module,
include_paths=module.include_dirs[:])
def __hash__(self):
return hash(self.path + self.library)
class VHDLFile(SourceFile):
def __init__(self, path, module, library=None, vcom_opt=None):
......@@ -64,8 +69,6 @@ class VHDLFile(SourceFile):
class VerilogFile(SourceFile):
def __init__(self, path, module, library=None, vlog_opt=None, include_dirs=None):
if not library:
library = "work"
SourceFile.__init__(self, path=path, module=module, library=library)
if not vlog_opt:
self.vlog_opt = ""
......@@ -122,6 +125,14 @@ class PPRFile(File):
# Xilinx PlanAhead Project
pass
class XPRFile(File):
# Xilinx Vivado Project
pass
class BDFile(File):
# Xilinx Block Design
pass
class XCOFile(File):
# Xilinx Core Generator File
pass
......@@ -251,6 +262,10 @@ class SourceFileFactory:
nf = XMPFile(path=path, module=module)
elif extension == 'ppr':
nf = PPRFile(path=path, module=module)
elif extension == 'xpr':
nf = XPRFile(path=path, module=module)
elif extension == 'bd':
nf = BDFile(path=path, module=module)
elif extension == 'xco':
nf = XCOFile(path=path, module=module)
elif extension == 'ldf':
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -56,7 +56,9 @@ run.command \
library.cfg
#target for performing local simulation
sim: sim_pre_cmd
local: sim_pre_cmd simulation sim_post_cmd
simulation:
""")
makefile_text_1 = makefile_tmplt_1.substitute(
top_module=top_module.top_module
......@@ -86,7 +88,7 @@ sim: sim_pre_cmd
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
#target for cleaning all intermediate stuff
......@@ -97,7 +99,7 @@ clean:
mrproper: clean
\t\trm -f *.vcd *.asdb
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
......
"""Common functionality shared by multiple tools."""
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
from makefile_writer import MakefileWriter
import os
import string
from string import Template
class VsimMakefileWriter(MakefileWriter):
"""A Makefile writer for simulation suitable for vsim based simulators.
Currently used by:
- Modelsim
- Riviera
"""
def __init__(self):
# additional global flags to pass to every invocation of these commands
self.vcom_flags = ["-quiet", ]
self.vsim_flags = []
self.vlog_flags = ["-quiet", ]
self.vmap_flags = []
# These are variables that will be set in the makefile
# The key is the variable name, and the value is the variable value
self.custom_variables = {}
# Additional sim dependencies (e.g. modelsim.ini)
self.additional_deps = []
# Additional things removed during a clean e.g. simulator temp files
self.additional_clean = []
# These are files copied into your working directory by a make rule
# The key is the filename, the value is the file source path
self.copy_rules = {}
super(VsimMakefileWriter, self).__init__()
def generate_simulation_makefile(self, fileset, top_module):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
"""
from srcfile import VerilogFile, VHDLFile, SVFile
self.vlog_flags.append(self.__get_rid_of_vsim_incdirs(top_module.vlog_opt))
tmp = """## variables #############################
PWD := $(shell pwd)
"""
self.write(tmp)
self.writeln()
for var, value in self.custom_variables.iteritems():
self.writeln("%s := %s" % (var, value))
self.writeln()
self.writeln("VCOM_FLAGS := %s" % (' '.join(self.vcom_flags)))
self.writeln("VSIM_FLAGS := %s" % (' '.join(self.vsim_flags)))
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
self.write(vl.rel_path() + " \\\n")
self.write("\n")
self.write("VERILOG_OBJ := ")
for vl in fileset.filter(VerilogFile):
# make a file compilation indicator (these .dat files are made even if
# the compilation process fails) and add an ending according to file's
# extension (.sv and .vhd files may have the same corename and this
# causes a mess
self.write(os.path.join(vl.library, vl.purename, "." + vl.purename + "_" + vl.extension()) + " \\\n")
self.write('\n')
libs = set(f.library for f in fileset)
self.write("VHDL_SRC := ")
for vhdl in fileset.filter(VHDLFile):
self.write(vhdl.rel_path() + " \\\n")
self.writeln()
# list vhdl objects (_primary.dat files)
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile):
# file compilation indicator (important: add _vhd ending)
self.write(os.path.join(vhdl.library, vhdl.purename, "." + vhdl.purename + "_" + vhdl.extension()) + " \\\n")
self.write('\n')
self.write('LIBS := ')
self.write(' '.join(libs))
self.write('\n')
# tell how to make libraries
self.write('LIB_IND := ')
self.write(' '.join([lib + "/." + lib for lib in libs]))
self.write('\n')
self.writeln("## rules #################################")
self.writeln()
self.writeln("local: sim_pre_cmd simulation sim_post_cmd")
self.writeln()
self.writeln("simulation: %s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)" % (' '.join(self.additional_deps)),)
self.writeln("$(VERILOG_OBJ) : " + ' '.join(self.additional_deps))
self.writeln("$(VHDL_OBJ): $(LIB_IND) " + ' '.join(self.additional_deps))
self.writeln()
simcommands = string.Template("""sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd:
\t\t${sim_post_cmd}
""")
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
else:
sim_post_cmd = ''
simcommands = simcommands.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd)
self.write(simcommands)
self.writeln()
for filename, filesource in self.copy_rules.iteritems():
self.write(self.__create_copy_rule(filename, filesource))
self.writeln("clean:")
tmp = "\t\trm -rf $(LIBS) " + ' '.join(self.additional_clean)
self.writeln(tmp)
self.writeln(".PHONY: clean sim_pre_cmd sim_post_cmd simulation")
self.writeln()
for lib in libs:
self.write(lib + "/." + lib + ":\n")
vmap_command = "vmap $(VMAP_FLAGS)"
self.write(' '.join(["\t(vlib", lib, "&&", vmap_command,
lib, "&&", "touch", lib + "/." + lib, ")"]))
self.write(' '.join(["||", "rm -rf", lib, "\n"]))
self.write('\n\n')
# rules for all _primary.dat files for sv
for vl in fileset.filter(VerilogFile):
self.write("%s: %s" % (os.path.join(vl.library, vl.purename, ".%s_%s" % (vl.purename, vl.extension())),
vl.rel_path())
)
for dep_file in [dfile for dfile in vl.depends_on if dfile is not vl]:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
# ##
# self.write("\t\tvlog -work "+vl.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
# self.write(" -sv ")
# incdir = "+incdir+"
# incdir += '+'.join(vl.include_dirs)
# incdir += " "
# self.write(incdir)
# self.writeln(vl.vlog_opt+" $<")
####
compile_template = Template("\t\tvlog -work ${library} $$(VLOG_FLAGS) ${sv_option} +incdir+${include_dirs} ${vlog_opt} $$<")
compile_line = compile_template.substitute(library=vl.library,
sv_option="-sv" if isinstance(vl, SVFile) else "",
include_dirs='+'.join(vl.include_dirs),
vlog_opt=vl.vlog_opt)
self.writeln(compile_line)
self.write("\t\t@mkdir -p $(dir $@)")
self.writeln(" && touch $@ \n\n")
self.write("\n")
# list rules for all _primary.dat files for vhdl
for vhdl in fileset.filter(VHDLFile):
lib = vhdl.library
purename = vhdl.purename
# each .dat depends on corresponding .vhd file
self.write("%s: %s" % (os.path.join(lib, purename, "." + purename + "_" + vhdl.extension()),
vhdl.rel_path())
)
for dep_file in vhdl.depends_on:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln(' '.join(["\t\tvcom $(VCOM_FLAGS)", vhdl.vcom_opt, "-work", lib, "$< "]))
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@ \n")
self.writeln()
def __create_copy_rule(self, name, src):
"""Get a Makefile rule named name, which depends on src, copying it to
the local directory."""
rule = """%s: %s
\t\tcp $< . 2>&1
""" % (name, src)
return rule
def __get_rid_of_vsim_incdirs(self, vlog_opt=""):
if not vlog_opt:
vlog_opt = ""
vlogs = vlog_opt.split(' ')
ret = []
for v in vlogs:
if not v.startswith("+incdir+"):
ret.append(v)
return ' '.join(ret)
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -61,7 +61,9 @@ $$(PROJECT)1.sty \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool
local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "prj_project open \"$$(PROJECT).ldf\"" > run.tcl
\t\techo "prj_run PAR -impl $$(PROJECT)" >> run.tcl
\t\techo "prj_run Export -impl $$(PROJECT) -task Bitgen" >> run.tcl
......@@ -72,7 +74,7 @@ local: syn_pre_cmd check_tool
check_tool:
\t\t${check_tool}
syn_post_cmd: local
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_cmd:
......@@ -87,7 +89,7 @@ clean:
mrproper:
\t\trm -f *.jed
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd local check_tool
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""")
if top_mod.syn_pre_cmd:
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -61,7 +61,9 @@ GHDL_CRAP := \
#target for performing local simulation
sim: sim_pre_cmd
local: sim_pre_cmd simulation sim_post_cmd
simulation:
""")
makefile_text_1 = makefile_tmplt_1.substitute(
......@@ -82,7 +84,7 @@ sim: sim_pre_cmd
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
#target for cleaning all intermediate stuff
......@@ -93,7 +95,7 @@ clean:
mrproper: clean
\t\trm -f *.vcd
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -48,6 +48,8 @@ FAMILY_NAMES = {
"XC6V": "Virtex6",
"XC5V": "Virtex5",
"XC4V": "Virtex4",
"XC7Z": "Zynq",
"XC7V": "Virtex7",
"XC7K": "Kintex7",
"XC7A": "Artix7"}
......@@ -116,23 +118,23 @@ class ToolControls(MakefileWriter):
remote_name_tmpl = "R_NAME:={0}"
files_tmpl = "FILES := {0}"
user_tmpl = user_tmpl.format("$(HDLMAKE_RSYNTH_USER)#take the value from the environment")
user_tmpl = user_tmpl.format("$(HDLMAKE_RSYNTH_USER)# take the value from the environment")
test_tmpl = """__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
\t@echo "Remote synthesis user is not set.\
\t@echo "Remote synthesis user is not set. \
You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
endif
ifeq (x$(SERVER),x)
\t@echo "Remote synthesis server is not set.\
\t@echo "Remote synthesis server is not set. \
You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
endif
ifeq (x$(ISE_PATH),x)
\t@echo "Remote synthesis server is not set.\
\t@echo "Remote synthesis server is not set. \
You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
endif
"""
if server is None:
server_tmpl = server_tmpl.format("$(HDLMAKE_RSYNTH_SERVER)#take the value from the environment")
server_tmpl = server_tmpl.format("$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment")
else:
server_tmpl = server_tmpl.format(server)
......@@ -150,7 +152,7 @@ endif
self.writeln(files_tmpl.format(' \\\n'.join([s.rel_path() for s in files])))
self.writeln("")
self.writeln("#target for running synthesis in the remote location")
self.writeln("remote: __test_for_remote_synthesis_variables __send __do_synthesis")
self.writeln("remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis")
self.writeln("__send_back: __do_synthesis")
self.writeln("__do_synthesis: __send")
self.writeln("__send: __test_for_remote_synthesis_variables")
......@@ -235,21 +237,29 @@ webtalk_pn.xml \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool
local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
generate_tcl:
\t\techo "project open $$(PROJECT)" > run.tcl
\t\techo "process run {Generate Programming File} -force rerun_all" >> run.tcl
\t\techo "process run {Synthesize - XST}" >> run.tcl
\t\techo "process run {Translate}" >> run.tcl
\t\techo "process run {Map}" >> run.tcl
\t\techo "process run {Place & Route}" >> run.tcl
\t\techo "process run {Generate Programming File}" >> run.tcl
synthesis:
\t\t${xtclsh_path} run.tcl
check_tool:
\t\t${check_tool}
syn_post_cmd: local
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_cmd:
\t\t${syn_pre_cmd}
#target for cleaing all intermediate stuff
#target for cleaning all intermediate stuff
clean:
\t\trm -f $$(ISE_CRAP)
\t\trm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
......@@ -258,7 +268,7 @@ clean:
mrproper:
\t\trm -f *.bit *.bin *.mcs
.PHONY: mrproper clean syn_pre_scipt syn_post_cmd local check_tool
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""")
if top_mod.syn_pre_cmd:
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Adrian Byszuk (adrian.byszuk@lnls.br)
......@@ -86,14 +86,16 @@ ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.vlog_opt) + """
"""
make_preambule_p2 = string.Template("""## rules #################################
sim: sim_pre_cmd xilinxsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) fuse
local: sim_pre_cmd simulation sim_post_cmd
simulation: xilinxsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) fuse
$$(VERILOG_OBJ): $$(LIB_IND) xilinxsim.ini
$$(VHDL_OBJ): $$(LIB_IND) xilinxsim.ini
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
xilinxsim.ini: $$(XILINX_INI_PATH)/xilinxsim.ini
......@@ -104,7 +106,7 @@ fuse:
clean:
\t\trm -rf ./xilinxsim.ini $$(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log \
isim.wdb isim_proj isim_proj.*
.PHONY: clean sim_pre_cmd sim_post_cmd
.PHONY: clean sim_pre_cmd sim_post_cmd simulation
""")
#open the file and write the above preambule (part 1)
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -70,10 +70,13 @@ class ToolControls(MakefileWriter):