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Hdlmake
Commit d342f521 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Merge remote-tracking branch 'origin/release-2.1'

parents aabe6c84 8bd44158
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Showing with 1470 additions and 505 deletions
docs/conf.py
View file @ d342f521
......@@ -46,16 +46,16 @@ master_doc = 'index'
# General information about the project.
project = u'hdlmake'
copyright = u'2014, CERN'
copyright = u'2013-2015, CERN'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# built documents.
#
# The short X.Y version.
version = '2.0'
version = '2.1'
# The full version, including alpha/beta/rc tags.
release = '2.0'
release = '2.1'
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
......
docs/index.rst
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This diff is collapsed.
hdlmake/__main__.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -103,9 +103,21 @@ def main():
#
# Load global tool object (global_mod.py)
#
if not top_mod.action:
logging.error("`action' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to handle the project")
quit()
if top_mod.action == "synthesis":
if not top_mod.syn_tool:
logging.error("`syn_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to synthesize the project")
quit()
tool_name = top_mod.syn_tool
elif top_mod.action == "simulation":
if not top_mod.sim_tool:
logging.error("`sim_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to simulate the project")
quit()
tool_name = top_mod.sim_tool
logging.info('import tool module: ' + tool_name)
try:
......@@ -209,7 +221,7 @@ def _get_parser():
"""
usage = """hdlmake [command] [options]"""
description = """Release 2014\n
description = """Version 2.1\n
To see optional arguments for particular command type:
hdlmake <command> --help
\0
......@@ -265,6 +277,9 @@ def _get_parser():
parser.add_argument("--generate-project-vhd", help="generate project.vhd file with a meta package describing the project",
dest="generate_project_vhd", default=False, action="store_true")
parser.add_argument("--force", help="force hdlmake to generate the makefile, even if the specified tool is missing", default=False, action="store_true")
parser.add_argument("--allow-unknown", dest="allow_unknown",
default=False, help="allow unknown option insertions in the child Manifests", action="store_true")
return parser
......
hdlmake/action/remote_synthesis.py
View file @ d342f521
......@@ -49,29 +49,29 @@ class GenerateRemoteSynthesisMakefile(Action):
self._generate_remote_synthesis_makefile(tool_object)
def _search_tcl_file(self, directory=None):
# This function is used in _generate_remote_ise_makefile
if directory is None:
directory = "."
filenames = os.listdir(directory)
tcls = []
for filename in filenames:
file_parts = filename.split('.')
if file_parts[len(file_parts)-1] == "tcl":
tcls.append(filename)
if len(tcls) == 0:
return None
if len(tcls) > 1:
logging.warning("Multiple tcls in the current directory: " + str(tcls) + "\n" +
"Picking the first one: " + tcls[0])
return tcls[0]
def _generate_tcl(self):
# This function is used in _generate_remote_ise_makefile
f = open("run.tcl", "w")
f.write("project open " + self.top_module.syn_project + '\n')
f.write("process run {Generate Programming File} -force rerun_all\n")
f.close()
#def _search_tcl_file(self, directory=None):
# # This function is used in _generate_remote_ise_makefile
# if directory is None:
# directory = "."
# filenames = os.listdir(directory)
# tcls = []
# for filename in filenames:
# file_parts = filename.split('.')
# if file_parts[len(file_parts)-1] == "tcl":
# tcls.append(filename)
# if len(tcls) == 0:
# return None
# if len(tcls) > 1:
# logging.warning("Multiple tcls in the current directory: " + str(tcls) + "\n" +
# "Picking the first one: " + tcls[0])
# return tcls[0]
#def _generate_tcl(self):
# # This function is used in _generate_remote_ise_makefile
# f = open("run.tcl", "w")
# f.write("project open " + self.top_module.syn_project + '\n')
# f.write("process run {Generate Programming File} -force rerun_all\n")
# f.close()
def _generate_remote_synthesis_makefile(self, tool_object):
......@@ -80,14 +80,14 @@ class GenerateRemoteSynthesisMakefile(Action):
top_mod = self.modules_pool.get_top_module()
tcl = self._search_tcl_file()
if tcl is None:
self._generate_tcl()
tcl = "run.tcl"
#tcl = self._search_tcl_file()
#if tcl is None:
# self._generate_tcl()
# tcl = "run.tcl"
files = self.modules_pool.build_global_file_set()
sff = SourceFileFactory()
files.add(sff.new(tcl, module=None))
files.add(sff.new("run.tcl", module=None))
files.add(sff.new(top_mod.syn_project, module=None))
tool_object.generate_remote_synthesis_makefile(files=files, name=top_mod.syn_name,
......
hdlmake/action/synthesis_project.py
View file @ d342f521
......@@ -148,7 +148,7 @@ end sdb_meta_pkg;""")
env = self.env
if not self.options.force:
if self.env[path_key] is None:
logging.error("Can't generate an " + name + " project. " + name + " not found.")
logging.error("Can't generate the " + name + " project. " + name + " not found.")
quit()
if not env[version_key]:
logging.error(name + " version cannot be deduced. Cannot generate " + name + " "
......
hdlmake/module.py
View file @ d342f521
......@@ -207,7 +207,10 @@ class Module(object):
allow_unknown = True
extra_context = {}
else:
allow_unknown = False
if global_mod.options.allow_unknown is True:
allow_unknown = True
else:
allow_unknown = False
extra_context = dict(global_mod.top_module.manifest_dict) # copy the dictionary
del extra_context["modules"]
del extra_context["files"]
......
hdlmake/srcfile.py
View file @ d342f521
......@@ -38,11 +38,16 @@ class SourceFile(DepFile):
assert isinstance(path, basestring)
assert isinstance(module, Module)
self.library = library
if not library:
self.library = "work"
DepFile.__init__(self,
file_path=path,
module=module,
include_paths=module.include_dirs[:])
def __hash__(self):
return hash(self.path + self.library)
class VHDLFile(SourceFile):
def __init__(self, path, module, library=None, vcom_opt=None):
......@@ -64,8 +69,6 @@ class VHDLFile(SourceFile):
class VerilogFile(SourceFile):
def __init__(self, path, module, library=None, vlog_opt=None, include_dirs=None):
if not library:
library = "work"
SourceFile.__init__(self, path=path, module=module, library=library)
if not vlog_opt:
self.vlog_opt = ""
......@@ -122,6 +125,14 @@ class PPRFile(File):
# Xilinx PlanAhead Project
pass
class XPRFile(File):
# Xilinx Vivado Project
pass
class BDFile(File):
# Xilinx Block Design
pass
class XCOFile(File):
# Xilinx Core Generator File
pass
......@@ -251,6 +262,10 @@ class SourceFileFactory:
nf = XMPFile(path=path, module=module)
elif extension == 'ppr':
nf = PPRFile(path=path, module=module)
elif extension == 'xpr':
nf = XPRFile(path=path, module=module)
elif extension == 'bd':
nf = BDFile(path=path, module=module)
elif extension == 'xco':
nf = XCOFile(path=path, module=module)
elif extension == 'ldf':
......
hdlmake/tools/aldec/aldec.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -56,7 +56,9 @@ run.command \
library.cfg
#target for performing local simulation
sim: sim_pre_cmd
local: sim_pre_cmd simulation sim_post_cmd
simulation:
""")
makefile_text_1 = makefile_tmplt_1.substitute(
top_module=top_module.top_module
......@@ -86,7 +88,7 @@ sim: sim_pre_cmd
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
#target for cleaning all intermediate stuff
......@@ -97,7 +99,7 @@ clean:
mrproper: clean
\t\trm -f *.vcd *.asdb
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
......
hdlmake/tools/common/__init__.py 0 → 100644
View file @ d342f521
"""Common functionality shared by multiple tools."""
hdlmake/tools/common/sim_makefile_support.py 0 → 100644
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
from makefile_writer import MakefileWriter
import os
import string
from string import Template
class VsimMakefileWriter(MakefileWriter):
"""A Makefile writer for simulation suitable for vsim based simulators.
Currently used by:
- Modelsim
- Riviera
"""
def __init__(self):
# additional global flags to pass to every invocation of these commands
self.vcom_flags = ["-quiet", ]
self.vsim_flags = []
self.vlog_flags = ["-quiet", ]
self.vmap_flags = []
# These are variables that will be set in the makefile
# The key is the variable name, and the value is the variable value
self.custom_variables = {}
# Additional sim dependencies (e.g. modelsim.ini)
self.additional_deps = []
# Additional things removed during a clean e.g. simulator temp files
self.additional_clean = []
# These are files copied into your working directory by a make rule
# The key is the filename, the value is the file source path
self.copy_rules = {}
super(VsimMakefileWriter, self).__init__()
def generate_simulation_makefile(self, fileset, top_module):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
"""
from srcfile import VerilogFile, VHDLFile, SVFile
self.vlog_flags.append(self.__get_rid_of_vsim_incdirs(top_module.vlog_opt))
tmp = """## variables #############################
PWD := $(shell pwd)
"""
self.write(tmp)
self.writeln()
for var, value in self.custom_variables.iteritems():
self.writeln("%s := %s" % (var, value))
self.writeln()
self.writeln("VCOM_FLAGS := %s" % (' '.join(self.vcom_flags)))
self.writeln("VSIM_FLAGS := %s" % (' '.join(self.vsim_flags)))
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
self.write(vl.rel_path() + " \\\n")
self.write("\n")
self.write("VERILOG_OBJ := ")
for vl in fileset.filter(VerilogFile):
# make a file compilation indicator (these .dat files are made even if
# the compilation process fails) and add an ending according to file's
# extension (.sv and .vhd files may have the same corename and this
# causes a mess
self.write(os.path.join(vl.library, vl.purename, "." + vl.purename + "_" + vl.extension()) + " \\\n")
self.write('\n')
libs = set(f.library for f in fileset)
self.write("VHDL_SRC := ")
for vhdl in fileset.filter(VHDLFile):
self.write(vhdl.rel_path() + " \\\n")
self.writeln()
# list vhdl objects (_primary.dat files)
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile):
# file compilation indicator (important: add _vhd ending)
self.write(os.path.join(vhdl.library, vhdl.purename, "." + vhdl.purename + "_" + vhdl.extension()) + " \\\n")
self.write('\n')
self.write('LIBS := ')
self.write(' '.join(libs))
self.write('\n')
# tell how to make libraries
self.write('LIB_IND := ')
self.write(' '.join([lib + "/." + lib for lib in libs]))
self.write('\n')
self.writeln("## rules #################################")
self.writeln()
self.writeln("local: sim_pre_cmd simulation sim_post_cmd")
self.writeln()
self.writeln("simulation: %s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)" % (' '.join(self.additional_deps)),)
self.writeln("$(VERILOG_OBJ) : " + ' '.join(self.additional_deps))
self.writeln("$(VHDL_OBJ): $(LIB_IND) " + ' '.join(self.additional_deps))
self.writeln()
simcommands = string.Template("""sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd:
\t\t${sim_post_cmd}
""")
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
else:
sim_post_cmd = ''
simcommands = simcommands.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd)
self.write(simcommands)
self.writeln()
for filename, filesource in self.copy_rules.iteritems():
self.write(self.__create_copy_rule(filename, filesource))
self.writeln("clean:")
tmp = "\t\trm -rf $(LIBS) " + ' '.join(self.additional_clean)
self.writeln(tmp)
self.writeln(".PHONY: clean sim_pre_cmd sim_post_cmd simulation")
self.writeln()
for lib in libs:
self.write(lib + "/." + lib + ":\n")
vmap_command = "vmap $(VMAP_FLAGS)"
self.write(' '.join(["\t(vlib", lib, "&&", vmap_command,
lib, "&&", "touch", lib + "/." + lib, ")"]))
self.write(' '.join(["||", "rm -rf", lib, "\n"]))
self.write('\n\n')
# rules for all _primary.dat files for sv
for vl in fileset.filter(VerilogFile):
self.write("%s: %s" % (os.path.join(vl.library, vl.purename, ".%s_%s" % (vl.purename, vl.extension())),
vl.rel_path())
)
for dep_file in [dfile for dfile in vl.depends_on if dfile is not vl]:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
# ##
# self.write("\t\tvlog -work "+vl.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
# self.write(" -sv ")
# incdir = "+incdir+"
# incdir += '+'.join(vl.include_dirs)
# incdir += " "
# self.write(incdir)
# self.writeln(vl.vlog_opt+" $<")
####
compile_template = Template("\t\tvlog -work ${library} $$(VLOG_FLAGS) ${sv_option} +incdir+${include_dirs} ${vlog_opt} $$<")
compile_line = compile_template.substitute(library=vl.library,
sv_option="-sv" if isinstance(vl, SVFile) else "",
include_dirs='+'.join(vl.include_dirs),
vlog_opt=vl.vlog_opt)
self.writeln(compile_line)
self.write("\t\t@mkdir -p $(dir $@)")
self.writeln(" && touch $@ \n\n")
self.write("\n")
# list rules for all _primary.dat files for vhdl
for vhdl in fileset.filter(VHDLFile):
lib = vhdl.library
purename = vhdl.purename
# each .dat depends on corresponding .vhd file
self.write("%s: %s" % (os.path.join(lib, purename, "." + purename + "_" + vhdl.extension()),
vhdl.rel_path())
)
for dep_file in vhdl.depends_on:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln(' '.join(["\t\tvcom $(VCOM_FLAGS)", vhdl.vcom_opt, "-work", lib, "$< "]))
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@ \n")
self.writeln()
def __create_copy_rule(self, name, src):
"""Get a Makefile rule named name, which depends on src, copying it to
the local directory."""
rule = """%s: %s
\t\tcp $< . 2>&1
""" % (name, src)
return rule
def __get_rid_of_vsim_incdirs(self, vlog_opt=""):
if not vlog_opt:
vlog_opt = ""
vlogs = vlog_opt.split(' ')
ret = []
for v in vlogs:
if not v.startswith("+incdir+"):
ret.append(v)
return ' '.join(ret)
hdlmake/tools/diamond/diamond.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -61,7 +61,9 @@ $$(PROJECT)1.sty \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool
local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "prj_project open \"$$(PROJECT).ldf\"" > run.tcl
\t\techo "prj_run PAR -impl $$(PROJECT)" >> run.tcl
\t\techo "prj_run Export -impl $$(PROJECT) -task Bitgen" >> run.tcl
......@@ -72,7 +74,7 @@ local: syn_pre_cmd check_tool
check_tool:
\t\t${check_tool}
syn_post_cmd: local
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_cmd:
......@@ -87,7 +89,7 @@ clean:
mrproper:
\t\trm -f *.jed
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd local check_tool
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""")
if top_mod.syn_pre_cmd:
......
hdlmake/tools/ghdl/ghdl.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -61,7 +61,9 @@ GHDL_CRAP := \
#target for performing local simulation
sim: sim_pre_cmd
local: sim_pre_cmd simulation sim_post_cmd
simulation:
""")
makefile_text_1 = makefile_tmplt_1.substitute(
......@@ -82,7 +84,7 @@ sim: sim_pre_cmd
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
#target for cleaning all intermediate stuff
......@@ -93,7 +95,7 @@ clean:
mrproper: clean
\t\trm -f *.vcd
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
......
hdlmake/tools/ise/ise.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -48,6 +48,8 @@ FAMILY_NAMES = {
"XC6V": "Virtex6",
"XC5V": "Virtex5",
"XC4V": "Virtex4",
"XC7Z": "Zynq",
"XC7V": "Virtex7",
"XC7K": "Kintex7",
"XC7A": "Artix7"}
......@@ -116,23 +118,23 @@ class ToolControls(MakefileWriter):
remote_name_tmpl = "R_NAME:={0}"
files_tmpl = "FILES := {0}"
user_tmpl = user_tmpl.format("$(HDLMAKE_RSYNTH_USER)#take the value from the environment")
user_tmpl = user_tmpl.format("$(HDLMAKE_RSYNTH_USER)# take the value from the environment")
test_tmpl = """__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
\t@echo "Remote synthesis user is not set.\
\t@echo "Remote synthesis user is not set. \
You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
endif
ifeq (x$(SERVER),x)
\t@echo "Remote synthesis server is not set.\
\t@echo "Remote synthesis server is not set. \
You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
endif
ifeq (x$(ISE_PATH),x)
\t@echo "Remote synthesis server is not set.\
\t@echo "Remote synthesis server is not set. \
You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
endif
"""
if server is None:
server_tmpl = server_tmpl.format("$(HDLMAKE_RSYNTH_SERVER)#take the value from the environment")
server_tmpl = server_tmpl.format("$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment")
else:
server_tmpl = server_tmpl.format(server)
......@@ -150,7 +152,7 @@ endif
self.writeln(files_tmpl.format(' \\\n'.join([s.rel_path() for s in files])))
self.writeln("")
self.writeln("#target for running synthesis in the remote location")
self.writeln("remote: __test_for_remote_synthesis_variables __send __do_synthesis")
self.writeln("remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis")
self.writeln("__send_back: __do_synthesis")
self.writeln("__do_synthesis: __send")
self.writeln("__send: __test_for_remote_synthesis_variables")
......@@ -235,21 +237,29 @@ webtalk_pn.xml \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool
local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
generate_tcl:
\t\techo "project open $$(PROJECT)" > run.tcl
\t\techo "process run {Generate Programming File} -force rerun_all" >> run.tcl
\t\techo "process run {Synthesize - XST}" >> run.tcl
\t\techo "process run {Translate}" >> run.tcl
\t\techo "process run {Map}" >> run.tcl
\t\techo "process run {Place & Route}" >> run.tcl
\t\techo "process run {Generate Programming File}" >> run.tcl
synthesis:
\t\t${xtclsh_path} run.tcl
check_tool:
\t\t${check_tool}
syn_post_cmd: local
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_cmd:
\t\t${syn_pre_cmd}
#target for cleaing all intermediate stuff
#target for cleaning all intermediate stuff
clean:
\t\trm -f $$(ISE_CRAP)
\t\trm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
......@@ -258,7 +268,7 @@ clean:
mrproper:
\t\trm -f *.bit *.bin *.mcs
.PHONY: mrproper clean syn_pre_scipt syn_post_cmd local check_tool
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""")
if top_mod.syn_pre_cmd:
......
hdlmake/tools/isim/isim.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Adrian Byszuk (adrian.byszuk@lnls.br)
......@@ -86,14 +86,16 @@ ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.vlog_opt) + """
"""
make_preambule_p2 = string.Template("""## rules #################################
sim: sim_pre_cmd xilinxsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) fuse
local: sim_pre_cmd simulation sim_post_cmd
simulation: xilinxsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) fuse
$$(VERILOG_OBJ): $$(LIB_IND) xilinxsim.ini
$$(VHDL_OBJ): $$(LIB_IND) xilinxsim.ini
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
xilinxsim.ini: $$(XILINX_INI_PATH)/xilinxsim.ini
......@@ -104,7 +106,7 @@ fuse:
clean:
\t\trm -rf ./xilinxsim.ini $$(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log \
isim.wdb isim_proj isim_proj.*
.PHONY: clean sim_pre_cmd sim_post_cmd
.PHONY: clean sim_pre_cmd sim_post_cmd simulation
""")
#open the file and write the above preambule (part 1)
......
hdlmake/tools/iverilog/iverilog.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -70,10 +70,13 @@ class ToolControls(MakefileWriter):
makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module}
IVERILOG_CRAP := \
run.command
run.command \
ivl_vhdl_work
#target for performing local simulation
sim: sim_pre_cmd
local: sim_pre_cmd simulation sim_post_cmd
simulation:
""")
makefile_text_1 = makefile_tmplt_1.substitute(
......@@ -99,7 +102,7 @@ sim: sim_pre_cmd
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
#target for cleaning all intermediate stuff
......@@ -110,7 +113,7 @@ clean:
mrproper: clean
\t\trm -f *.vcd *.vvp
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
if top_module.sim_pre_cmd:
......
hdlmake/tools/libero/libero.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -61,7 +61,9 @@ LIBERO_CRAP := \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool
local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "open_project -file {$$(PROJECT)/$$(PROJECT).prjx}" > run.tcl
\t\techo "update_and_run_tool -name {GENERATEPROGRAMMINGDATA}" >> run.tcl
\t\techo "save_project" >> run.tcl
......@@ -72,7 +74,7 @@ local: syn_pre_cmd check_tool
check_tool:
\t\t${check_tool}
syn_post_cmd: local
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_cmd:
......@@ -87,7 +89,7 @@ clean:
mrproper:
\t\trm -f *.pdb *.stp
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd local check_tool
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""")
if top_mod.syn_pre_cmd:
......
hdlmake/tools/modelsim/modelsim.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -33,15 +33,16 @@ import string
from string import Template
import fetch
from makefile_writer import MakefileWriter
from .. common.sim_makefile_support import VsimMakefileWriter
XmlImpl = xml.dom.minidom.getDOMImplementation()
MODELSIM_STANDARD_LIBS = ['ieee', 'std']
class ToolControls(MakefileWriter):
class ToolControls(VsimMakefileWriter):
def __init__(self):
super(ToolControls, self).__init__()
def detect_version(self, path):
pass
......@@ -60,164 +61,17 @@ class ToolControls(MakefileWriter):
return MODELSIM_STANDARD_LIBS
def generate_simulation_makefile(self, fileset, top_module):
from srcfile import VerilogFile, VHDLFile, SVFile
make_preambule_p1 = """## variables #############################
PWD := $(shell pwd)
MODELSIM_INI_PATH := {0}
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini """ + self.__get_rid_of_vsim_incdirs(top_module.vlog_opt) + """
"""
self.vcom_flags.extend(["-modelsimini", "modelsim.ini"])
self.vlog_flags.extend(["-modelsimini", "modelsim.ini"])
self.vmap_flags.extend(["-modelsimini", "modelsim.ini"])
if global_mod.env["modelsim_path"]:
make_preambule_p1 = make_preambule_p1.format(os.path.join(global_mod.env["modelsim_path"], ".."))
modelsim_ini_path = os.path.join(global_mod.env["modelsim_path"], "..")
else:
make_preambule_p1 = make_preambule_p1.format(os.path.join("$(HDLMAKE_MODELSIM_PATH)", ".."))
make_preambule_p2 = string.Template("""## rules #################################
sim: sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
$$(VERILOG_OBJ): $$(VHDL_OBJ)
$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
\t\t${sim_post_cmd}
modelsim.ini: ${modelsim_ini_path}
\t\tcp $$< . 2>&1
clean:
\t\trm -rf ./modelsim.ini $$(LIBS) transcript *.vcd *.wlf
.PHONY: clean sim_pre_cmd sim_post_cmd
""")
#open the file and write the above preambule (part 1)
self.write(make_preambule_p1)
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
self.write(vl.rel_path() + " \\\n")
self.write("\n")
self.write("VERILOG_OBJ := ")
for vl in fileset.filter(VerilogFile):
#make a file compilation indicator (these .dat files are made even if
#the compilation process fails) and add an ending according to file's
#extension (.sv and .vhd files may have the same corename and this
#causes a mess
self.write(os.path.join(vl.library, vl.purename, "."+vl.purename+"_"+vl.extension()) + " \\\n")
self.write('\n')
libs = set(f.library for f in fileset)
self.write("VHDL_SRC := ")
for vhdl in fileset.filter(VHDLFile):
self.write(vhdl.rel_path() + " \\\n")
self.writeln()
#list vhdl objects (_primary.dat files)
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile):
#file compilation indicator (important: add _vhd ending)
self.write(os.path.join(vhdl.library, vhdl.purename, "."+vhdl.purename+"_"+vhdl.extension()) + " \\\n")
self.write('\n')
self.write('LIBS := ')
self.write(' '.join(libs))
self.write('\n')
#tell how to make libraries
self.write('LIB_IND := ')
self.write(' '.join([lib+"/."+lib for lib in libs]))
self.write('\n')
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
else:
sim_post_cmd = ''
make_preambule_p2 = make_preambule_p2.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd,
modelsim_ini_path=os.path.join("$(MODELSIM_INI_PATH)", "modelsim.ini"))
self.write(make_preambule_p2)
for lib in libs:
self.write(lib+"/."+lib+":\n")
self.write(' '.join(["\t(vlib", lib, "&&", "vmap", "-modelsimini modelsim.ini",
lib, "&&", "touch", lib+"/."+lib, ")"]))
self.write(' '.join(["||", "rm -rf", lib, "\n"]))
self.write('\n')
#rules for all _primary.dat files for sv
for vl in fileset.filter(VerilogFile):
self.write("%s: %s" % (os.path.join(vl.library, vl.purename, ".%s_%s" % (vl.purename, vl.extension())),
vl.rel_path())
)
for dep_file in [dfile for dfile in vl.depends_on if dfile is not vl]:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
###
# self.write("\t\tvlog -work "+vl.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
# self.write(" -sv ")
# incdir = "+incdir+"
# incdir += '+'.join(vl.include_dirs)
# incdir += " "
# self.write(incdir)
# self.writeln(vl.vlog_opt+" $<")
####
compile_template = Template("\t\tvlog -work ${library} $$(VLOG_FLAGS) ${sv_option} +incdir+${include_dirs} ${vlog_opt} $$<")
compile_line = compile_template.substitute(library=vl.library,
sv_option = "-sv" if isinstance(vl, SVFile) else "",
include_dirs='+'.join(vl.include_dirs),
vlog_opt=vl.vlog_opt)
self.writeln(compile_line)
self.write("\t\t@mkdir -p $(dir $@)")
self.writeln(" && touch $@ \n\n")
self.write("\n")
#list rules for all _primary.dat files for vhdl
for vhdl in fileset.filter(VHDLFile):
lib = vhdl.library
purename = vhdl.purename
#each .dat depends on corresponding .vhd file
self.write("%s: %s" % (os.path.join(lib, purename, "."+purename+"_" + vhdl.extension()),
vhdl.rel_path())
)
for dep_file in vhdl.depends_on:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" % (name, extension)))
else: #the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln(' '.join(["\t\tvcom $(VCOM_FLAGS)", vhdl.vcom_opt, "-work", lib, "$< "]))
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@\n")
self.writeln()
modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")
self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
self.additional_deps.append("modelsim.ini")
self.additional_clean.extend(["./modelsim.ini", "transcript", "*.vcd", "*.wlf"])
def __get_rid_of_vsim_incdirs(self, vlog_opt):
if not vlog_opt:
vlog_opt = ""
vlogs = vlog_opt.split(' ')
ret = []
for v in vlogs:
if not v.startswith("+incdir+"):
ret.append(v)
return ' '.join(ret)
self.copy_rules["modelsim.ini"] = os.path.join("$(MODELSIM_INI_PATH)", "modelsim.ini")
super(ToolControls, self).generate_simulation_makefile(fileset, top_module)
hdlmake/tools/planahead/planahead.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -64,7 +64,9 @@ planAhead.* \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool
local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "open_project $$(PROJECT).ppr" > run.tcl
\t\techo "reset_run synth_1" >> run.tcl
\t\techo "reset_run impl_1" >> run.tcl
......@@ -81,7 +83,7 @@ local: syn_pre_cmd check_tool
check_tool:
\t\t${check_tool}
syn_post_cmd: local
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_cmd:
......@@ -96,7 +98,7 @@ clean:
mrproper:
\t\trm -f *.bit
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd local check_tool
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""")
if top_mod.syn_pre_cmd:
......
hdlmake/tools/quartus/quartus.py
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -73,7 +73,9 @@ $$(PROJECT).sta.summary \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool
local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "load_package flow" > run.tcl
\t\techo "project_open $$(PROJECT)" >> run.tcl
\t\techo "execute_flow -compile" >> run.tcl
......@@ -82,7 +84,7 @@ local: syn_pre_cmd check_tool
check_tool:
\t\t${check_tool}
syn_post_cmd: local
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_cmd:
......@@ -97,7 +99,7 @@ clean:
mrproper:
\t\trm -f *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd local check_tool
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""")
if top_mod.syn_pre_cmd:
......
hdlmake/tools/riviera/riviera.py 0 → 100644
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# Riviera tool added by Josh Smith (joshrsmith@gmail.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
from __future__ import print_function
from .. common.sim_makefile_support import VsimMakefileWriter
# as of 2014.06, these are the standard libraries
# included in an installation
RIVIERA_STANDARD_LIBS = [
'ieee', 'std', 'cpld',
'vl', 'vital95', 'vital2000',
'synopsys', 'aldec', 'vtl',
'vtl_dbg', 'assertions', 'ieee_proposed',
'ovm_2_0_3', 'ovm_2_1_2', 'uvm_1_0p1',
'uvm_1_1d', 'uvm', 'osvvm',
]
# there are many vendor specific libraries available
# a few of them are listed here
RIVIERA_XILINX_VHDL_LIBRARIES = [
'cpld',
'secureip',
'simprim',
'unimacro',
'unisim',
'xilinxcorelib'
]
RIVIERA_XILINX_VLOG_LIBRARIES = [
'cpld_ver',
'secureip',
'simprims_ver',
'uni9000_ver',
'unimacro_ver',
'unisims_ver',
'xilinxcorelib_ver'
]
RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VHDL_LIBRARIES)
RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES)
class ToolControls(VsimMakefileWriter):
def __init__(self):
super(ToolControls, self).__init__()
self.vcom_flags.append("-2008")
self.additional_clean.extend(["*.asdb", "*.vcd", ])
def detect_version(self, path):
pass
def get_keys(self):
tool_info = {
'name': 'Riviera',
'id': 'riviera',
'windows_bin': 'vsim',
'linux_bin': 'vsim'
}
return tool_info
def get_standard_libraries(self):
return RIVIERA_STANDARD_LIBS
hdlmake/tools/vivado/vivado.py 0 → 100644
View file @ d342f521
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
import subprocess
import sys
import os
import string
from string import Template
import fetch
import logging
from makefile_writer import MakefileWriter
VIVADO_STANDARD_LIBS = ['ieee', 'std']
class ToolControls(MakefileWriter):
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'vivado',
'id': 'vivado',
'windows_bin': 'vivado',
'linux_bin': 'vivado',
'project_ext': 'xpr'
}
return tool_info
def get_standard_libraries(self):
return VIVADO_STANDARD_LIBS
def generate_synthesis_makefile(self, top_mod, tool_path):
makefile_tmplt = string.Template("""PROJECT := ${project_name}
VIVADO_CRAP := \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool synthesis syn_post_cmd
synthesis:
\t\techo "open_project $$(PROJECT).xpr" > run.tcl
\t\techo "reset_run synth_1" >> run.tcl
\t\techo "reset_run impl_1" >> run.tcl
\t\techo "launch_runs synth_1" >> run.tcl
\t\techo "wait_on_run synth_1" >> run.tcl
\t\techo "launch_runs impl_1" >> run.tcl
\t\techo "wait_on_run impl_1" >> run.tcl
\t\techo "launch_runs impl_1 -to_step write_bitstream" >> run.tcl
\t\techo "wait_on_run impl_1" >> run.tcl
\t\techo "exit" >> run.tcl
\t\t${vivado_sh_path} -mode tcl -source run.tcl
\t\tcp $$(PROJECT).runs/impl_1/${syn_top}.bit ${syn_top}.bit
check_tool:
\t\t${check_tool}
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_cmd:
\t\t${syn_pre_cmd}
#target for cleaning all intermediate stuff
clean:
\t\trm -f $$(PLANAHEAD_CRAP)
\t\trm -rf .Xil $$(PROJECT).cache $$(PROJECT).data $$(PROJECT).runs $$(PROJECT).xpr
#target for cleaning final files
mrproper:
\t\trm -f *.bit
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
""")
if top_mod.syn_pre_cmd:
syn_pre_cmd = top_mod.syn_pre_cmd
else:
syn_pre_cmd = ''
if top_mod.syn_post_cmd:
syn_post_cmd = top_mod.syn_post_cmd
else:
syn_post_cmd = ''
if top_mod.force_tool:
ft = top_mod.force_tool
check_tool = """python $(HDLMAKE_HDLMAKE_PATH)/hdlmake _conditioncheck --tool {tool} --reference {reference} --condition "{condition}"\\
|| (echo "{tool} version does not meet condition: {condition} {reference}" && false)
""".format(tool=ft[0],
condition=ft[1],
reference=ft[2])
else:
check_tool = ''
makefile_text = makefile_tmplt.substitute(syn_top=top_mod.syn_top,
project_name=top_mod.syn_project,
planahead_path=tool_path,
check_tool=check_tool,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd,
vivado_sh_path=os.path.join(tool_path, "vivado"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
def generate_remote_synthesis_makefile(self, files, name, cwd, user, server):
logging.info("Remote Vivado wrapper")
def generate_synthesis_project(self, update=False, tool_version='', top_mod=None, fileset=None):
self.properties = []
self.files = []
self.filename = top_mod.syn_project
self.header = None
self.tclname = 'temporal.tcl'
if update is True:
logging.info("Existing project detected: updating...")
self.update_project()
else:
logging.info("No previous project: creating a new one...")
self.create_project()
self.add_initial_properties(top_mod.syn_device,
top_mod.syn_grade,
top_mod.syn_package,
top_mod.syn_top)
self.add_files(fileset)
self.emit()
self.execute()
logging.info("Vivado project file generated.")
def emit(self):
f = open(self.tclname, "w")
f.write(self.header+'\n')
for p in self.properties:
f.write(p.emit()+'\n')
f.write(self.__emit_files())
f.write('update_compile_order -fileset sources_1\n')
f.write('update_compile_order -fileset sim_1\n')
f.write('exit\n')
f.close()
def execute(self):
tmp = 'vivado -mode tcl -source {0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
## But do not wait till Vivado finish, start displaying output immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() != None:
break
if out != '':
sys.stdout.write(out)
sys.stdout.flush()
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
def add_property(self, new_property):
self.properties.append(new_property)
def add_initial_properties(self,
syn_device,
syn_grade,
syn_package,
syn_top):
PAPP = _VivadoProjectProperty
self.add_property(PAPP(name='part', value=syn_device+syn_package+syn_grade, objects='current_project'))
# self.add_property(PAPP(name='board_part', value='em.avnet.com:microzed_7010:part0:1.0', objects='current_project'))
self.add_property(PAPP(name='target_language', value='VHDL', objects='current_project'))
# self.add_property(PAPP(name='ng.output_hdl_format', value='VHDL', objects='get_filesets sim_1'))
# the bitgen b arg generates a raw configuration bitstream
# self.add_property(PAPP(name='steps.bitgen.args.b', value='true', objects='get_runs impl_1'))
self.add_property(PAPP(name='top', value=syn_top, objects='get_property srcset [current_run]'))
def create_project(self):
tmp = 'create_project {0} ./'
self.header = tmp.format(self.filename)
def update_project(self):
tmp = 'open_project ./{0}'
self.header = tmp.format(self.filename+'.xpr')
def __emit_properties(self):
tmp = "set_property {0} {1} [{2}]"
ret = []
for p in self.properties:
line = tmp.format(p.name, p.value, p.objects)
ret.append(line)
return ('\n'.join(ret))+'\n'
def __emit_files(self):
tmp = "add_files -norecurse {0}"
tcl = "source {0}"
ret = []
from srcfile import VHDLFile, VerilogFile, SVFile, UCFFile, NGCFile, XMPFile, XCOFile, BDFile, TCLFile
for f in self.files:
if isinstance(f, VHDLFile) or isinstance(f, VerilogFile) or isinstance(f, SVFile) or isinstance(f, UCFFile) or isinstance(f, NGCFile) or isinstance(f, XMPFile) or isinstance(f, XCOFile) or isinstance(f, BDFile):
line = tmp.format(f.rel_path())
elif isinstance(f, TCLFile):
line = tcl.format(f.rel_path())
else:
continue
ret.append(line)
return ('\n'.join(ret))+'\n'
class _VivadoProjectProperty:
def __init__(self, name=None, value=None, objects=None):
self.name = name
self.value = value
self.objects = objects
def emit(self):
tmp = "set_property {0} {1} [{2}]"
line = tmp.format(self.name, self.value, self.objects)
return(line)
hdlmake/vhdl_parser.py
View file @ d342f521
This diff is collapsed.
hdlmake/vlog_parser.py
View file @ d342f521
......@@ -34,19 +34,11 @@ from srcfile import SourceFileFactory
class VerilogPreprocessor(object):
# Reserved verilog preprocessor keywords. The list is certainly not full
# Reserved verilog preprocessor keywords. The list is certainly not full
vpp_keywords = ["define", "line", "include", "elsif", "ifdef", "endif", "else", "undef", "timescale"]
# List of `include search paths
vpp_searchdir = ["."]
# List of macro definitions
vpp_macros = []
# Dictionary of files sub-included by each file parsed
vpp_filedeps = {}
# Verilog `define class
# Verilog `define class
class VL_Define(object):
def __init__(self, name, args, expansion):
self.name = name
......@@ -73,6 +65,13 @@ class VerilogPreprocessor(object):
def __init__(self):
self.vpp_stack = self.VL_Stack()
self.vlog_file = None
# List of `include search paths
self.vpp_searchdir = ["."]
# List of macro definitions
self.vpp_macros = []
# Dictionary of files sub-included by each file parsed
self.vpp_filedeps = {}
def _find_macro(self, name):
for m in self.vpp_macros:
......@@ -137,7 +136,7 @@ class VerilogPreprocessor(object):
self.vpp_macros.append(mdef)
return mdef
def _preprocess_file(self, file_content, file_name):
def _preprocess_file(self, file_content, file_name, library):
exps = {"include": re.compile("^\s*`include\s+\"(.+)\""),
"define": re.compile("^\s*`define\s+(\w+)(?:\(([\w\s,]*)\))?(.*)"),
"ifdef_elsif": re.compile("^\s*`(ifdef|ifndef|elsif)\s+(\w+)\s*$"),
......@@ -145,11 +144,11 @@ class VerilogPreprocessor(object):
vl_macro_expand = re.compile("`(\w+)(?:\(([\w\s,]*)\))?")
# init dependencies
self.vpp_filedeps[file_name] = []
self.vpp_filedeps[file_name + library] = []
cur_iter = 0
logging.debug("preprocess file %s (of length %d)" % (file_name, len(file_content)))
logging.debug("preprocess file %s (of length %d) in library %s" % (file_name, len(file_content), library))
# print("BUF '%s'" %buf)
buf = self._remove_comment(file_content)
while True:
......@@ -188,12 +187,12 @@ class VerilogPreprocessor(object):
if matches["include"]:
included_file_path = self._search_include(last.group(1), os.path.dirname(file_name))
logging.debug("File being parsed %s includes %s" % (file_name, included_file_path))
logging.debug("File being parsed %s (library %s) includes %s" % (file_name, library, included_file_path))
line = self._preprocess_file(file_content=open(included_file_path, "r").read(),
file_name=included_file_path)
self.vpp_filedeps[file_name].append(included_file_path)
file_name=included_file_path, library=library)
self.vpp_filedeps[file_name + library].append(included_file_path)
# add the whole include chain to the dependencies of the currently parsed file
self.vpp_filedeps[file_name].extend(self.vpp_filedeps[included_file_path])
self.vpp_filedeps[file_name + library].extend(self.vpp_filedeps[included_file_path + library])
new_buf += line + '\n'
n_expansions += 1
continue
......@@ -235,7 +234,7 @@ class VerilogPreprocessor(object):
self.vlog_file = vlog_file
file_path = vlog_file.file_path
buf = open(file_path, "r").read()
return self._preprocess_file(file_content=buf, file_name=file_path)
return self._preprocess_file(file_content=buf, file_name=file_path, library = vlog_file.library)
def _find_first(self, f, l):
x = filter(f, l)
......@@ -535,6 +534,7 @@ class VerilogParser(DepParser):
return buf2
def parse(self, dep_file):
i = 0;
if dep_file.is_parsed:
return
logging.info("Parsing %s" % dep_file.path)
......@@ -544,7 +544,7 @@ class VerilogParser(DepParser):
#add includes as dependencies
try:
includes = self.preprocessor.vpp_filedeps[dep_file.path]
includes = self.preprocessor.vpp_filedeps[dep_file.path + dep_file.library]
for f in includes:
dep_file.depends_on.add(SourceFileFactory().new(path=f, module=dep_file.module))
logging.debug( "%s has %d includes." % (str(dep_file), len(includes)))
......@@ -561,15 +561,15 @@ class VerilogParser(DepParser):
#and HdlMake will anyway create dependency marking my_other_module as requested package
import_pattern = re.compile("(\w+) *::(\w+|\\*)")
def do_imports(s):
logging.debug("file %s imports/uses %s package" %( dep_file.path , s.group(1) ) )
dep_file.add_relation(DepRelation(s.group(1), DepRelation.USE, DepRelation.PACKAGE))
logging.debug("file %s imports/uses %s.%s package" %( dep_file.path , dep_file.library, s.group(1) ) )
dep_file.add_relation( DepRelation( "%s.%s" % (dep_file.library, s.group(1)) , DepRelation.USE, DepRelation.PACKAGE))
re.subn(import_pattern, do_imports, buf)
#packages
m_inside_package = re.compile("package\s+(\w+)\s*(?:\(.*?\))?\s*(.+?)endpackage", re.DOTALL | re.MULTILINE)
def do_package(s):
logging.debug("found pacakge %s" %s.group(1))
dep_file.add_relation(DepRelation(s.group(1), DepRelation.PROVIDE, DepRelation.PACKAGE))
logging.debug("found pacakge %s.%s" %(dep_file.library, s.group(1)) )
dep_file.add_relation(DepRelation( "%s.%s" % (dep_file.library, s.group(1)), DepRelation.PROVIDE, DepRelation.PACKAGE))
re.subn(m_inside_package, do_package, buf)
#modules and instatniations
......@@ -577,15 +577,15 @@ class VerilogParser(DepParser):
m_instantiation = re.compile("(?:\A|\\s*)\s*(\w+)\s+(?:#\s*\(.*?\)\s*)?(\w+)\s*\(.*?\)\s*", re.DOTALL | re.MULTILINE)
def do_module(s):
logging.debug("found module %s" %s.group(1))
dep_file.add_relation(DepRelation(s.group(1), DepRelation.PROVIDE, DepRelation.ENTITY))
logging.debug("found module %s.%s" % (dep_file.library, s.group(1) ))
dep_file.add_relation(DepRelation( "%s.%s" % (dep_file.library, s.group(1)), DepRelation.PROVIDE, DepRelation.ENTITY))
def do_inst(s):
mod_name = s.group(1)
if(mod_name in self.reserved_words):
return
logging.debug("-> instantiates %s as %s" % (s.group(1), s.group(2) ))
dep_file.add_relation(DepRelation(s.group(1), DepRelation.USE, DepRelation.ENTITY))
logging.debug("-> instantiates %s.%s as %s" % (dep_file.library, s.group(1), s.group(2) ))
dep_file.add_relation(DepRelation( "%s.%s" % (dep_file.library, s.group(1)), DepRelation.USE, DepRelation.ENTITY))
re.subn(m_instantiation, do_inst, s.group(2))
re.subn(m_inside_module, do_module, buf)
......
tests/counter/sim/iverilog/vhdl/Manifest.py 0 → 100644
View file @ d342f521
action = "simulation"
sim_tool = "iverilog"
top_module = "counter_tb"
sim_pre_cmd ="echo IMPORTANT, IVerilog always needs a Verilog testbench, no matter if the DUT is written in VHDL!"
sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"
files = [
"../../../modules/counter/vhdl/counter.vhd",
"../../../testbench/counter_tb/verilog/counter_tb.v",
]
tests/counter/sim/riviera/verilog/Manifest.py 0 → 100644
View file @ d342f521
action = "simulation"
sim_tool = "riviera"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
tests/counter/sim/riviera/vhdl/Manifest.py 0 → 100644
View file @ d342f521
action = "simulation"
sim_tool = "riviera"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
tests/counter/sim/riviera/vsim.do 0 → 100644
View file @ d342f521
vsim counter_tb +access +r;
add wave *;
run 6000ns;
tests/questa_uvm_sv/rtl/Manifest.py
View file @ d342f521
include_dirs = "./include"
files = ["include/includeModule.sv",
files = ["include/includeModuleSV.sv",
"include/includeModuleVHDL.vhdl",
"include/includeModuleAVHDL.vhdl",
"include/includeModuleBVHDL.vhdl",
"RTL_SVPackage.sv",
"RTLTopModuleSV.sv",
"RTLTopModuleVerilogSimulationModel.vo",
......
tests/questa_uvm_sv/rtl/RTLTopModuleSV.sv
View file @ d342f521
......@@ -14,7 +14,7 @@ module RTLTopModuleSV;
initial
l1a <= RTL_SVPackage::CONST;
includeModule incl();
includeModuleSV incl();
ipcore ip();
endmodule // RTLTopModuleSV
tests/questa_uvm_sv/rtl/RTLTopModuleVHDL.vhdl
View file @ d342f521
-------------------------------------------------------------------------------
-- Title : RTLTopModuleVHDL
-- Project :
-- Title : RTLTopModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : RTLTopModuleVHDL.vhdl
-- Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch>
-- Company : CERN
-- Created : 2014-09-26
-- Last update: 2014-09-26
-- Platform :
-- Standard : VHDL'2008
-- File : RTLTopModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation, either version 3 of the License, or any later version.
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-09-26 1.0 afiergol Created
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RTLTopModuleVHDL is
end entity RTLTopModuleVHDL;
architecture Behavioral of RTLTopModuleVHDL is
component includeModuleVHDL is
end component;
signal probe : STD_LOGIC;
begin -- architecture Behavioral
begin -- architectureecture Behavioral
probe <= '1';
include_module : includeModuleVHDL;
a : entity work.includeModuleAVHDL;
GEN : for i in 0 to 3 generate
B : entity work.includeModuleBVHDL;
end generate;
end architecture Behavioral;
tests/questa_uvm_sv/rtl/include/includeModuleAVHDL.vhdl 0 → 100644
View file @ d342f521
-------------------------------------------------------------------------------
-- Title : includeModuleAVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleAVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleAVHDL is
end entity includeModuleAVHDL;
architecture Behavioral of includeModuleAVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
tests/questa_uvm_sv/rtl/include/includeModuleBVHDL.vhdl 0 → 100644
View file @ d342f521
-------------------------------------------------------------------------------
-- Title : includeModuleBVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleBVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleBVHDL is
end entity includeModuleBVHDL;
architecture Behavioral of includeModuleBVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
tests/questa_uvm_sv/rtl/include/includeModule.sv → tests/questa_uvm_sv/rtl/include/includeModuleSV.sv
View file @ d342f521
// -*- Mode: Verilog -*-
// Filename : includeModule.sv
// Filename : includeModuleSV.sv
// Description : Included submodule
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:51:41 2014
......@@ -8,7 +8,7 @@
// Update Count : 0
// Status : Unknown, Use with caution!
module includeModule;
module includeModuleSV;
endmodule // includeModule
endmodule // includeModuleSV
tests/questa_uvm_sv/rtl/include/includeModuleVHDL.vhdl 0 → 100644
View file @ d342f521
-------------------------------------------------------------------------------
-- Title : includeModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleVHDL is
end entity includeModuleVHDL;
architecture Behavioral of includeModuleVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
tests/questa_uvm_sv/sim/tests/Makefile
View file @ d342f521
......@@ -6,94 +6,121 @@
## variables #############################
PWD := $(shell pwd)
MODELSIM_INI_PATH := /opt/questa_sv_afv_10.3c_1/questasim//bin/..
MODELSIM_INI_PATH := /opt/questa_sv_afv_10.4/questasim//bin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC := ../../rtl/RTL_SVPackage.sv \
../../rtl/include/includeModule.sv \
../../ipcores/ipcore/ipcore.sv \
../../rtl/RTLTopModuleSV.sv \
../../rtl/RTLTopModuleVerilogSimulationModel.vo \
VERILOG_SRC := ../../ipcores/ipcore/ipcore.sv \
../../rtl/RTL_SVPackage.sv \
src/genericTest.sv \
../../rtl/RTLTopModuleVerilogSimulationModel.vo \
../../rtl/include/includeModuleSV.sv \
../../rtl/RTLTopModuleSV.sv \
VERILOG_OBJ := work/RTL_SVPackage/.RTL_SVPackage_sv \
work/includeModule/.includeModule_sv \
work/ipcore/.ipcore_sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
VERILOG_OBJ := work/ipcore/.ipcore_sv \
work/RTL_SVPackage/.RTL_SVPackage_sv \
work/genericTest/.genericTest_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
work/includeModuleSV/.includeModuleSV_sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
VHDL_SRC := ../../rtl/RTLTopModuleVHDL.vhdl \
VHDL_SRC := ../../rtl/include/includeModuleBVHDL.vhdl \
../../rtl/include/includeModuleVHDL.vhdl \
../../rtl/include/includeModuleAVHDL.vhdl \
../../rtl/RTLTopModuleVHDL.vhdl \
VHDL_OBJ := work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl \
VHDL_OBJ := work/includeModuleBVHDL/.includeModuleBVHDL_vhdl \
work/includeModuleVHDL/.includeModuleVHDL_vhdl \
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl \
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl \
LIBS := work
LIB_IND := work/.work
## rules #################################
sim: sim_pre_cmd modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
local: sim_pre_cmd simulation sim_post_cmd
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
sim_pre_cmd:
sim_post_cmd: sim
sim_post_cmd:
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
clean:
rm -rf ./modelsim.ini $(LIBS)
.PHONY: clean sim_pre_cmd sim_post_cmd
rm -rf ./modelsim.ini $(LIBS) transcript *.vcd *.wlf
.PHONY: clean sim_pre_cmd sim_post_cmd simulation
work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/ipcore/.ipcore_sv: ../../ipcores/ipcore/ipcore.sv \
../../ipcores/ipcore/include/ipcoreInclude.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../ipcores/ipcore/include+../../ipcores/ipcore $<
@mkdir -p $(dir $@) && touch $@
work/RTL_SVPackage/.RTL_SVPackage_sv: ../../rtl/RTL_SVPackage.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/includeModule/.includeModule_sv: ../../rtl/include/includeModule.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl/include $<
work/genericTest/.genericTest_sv: src/genericTest.sv \
../environment/env.sv \
../sequences/sequence.sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
src/FullTest_pkg.sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
../environment/top.sv \
../environment/Env_pkg.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../environment+../sequences+src +incdir+../../mvc//questa_mvc_src/sv+../../mvc/questa_mvc_src/sv/mvc_base+../../mvc/include+../../uvm-1.1d/src $<
@mkdir -p $(dir $@) && touch $@
work/ipcore/.ipcore_sv: ../../ipcores/ipcore/ipcore.sv \
../../ipcores/ipcore/include/ipcoreInclude.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../ipcores/ipcore/include+../../ipcores/ipcore $<
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo: ../../rtl/RTLTopModuleVerilogSimulationModel.vo
vlog -work work $(VLOG_FLAGS) +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleSV/.includeModuleSV_sv: ../../rtl/include/includeModuleSV.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl/include $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleSV/.RTLTopModuleSV_sv: ../../rtl/RTLTopModuleSV.sv \
work/RTL_SVPackage/.RTL_SVPackage_sv \
work/includeModule/.includeModule_sv \
work/ipcore/.ipcore_sv
work/ipcore/.ipcore_sv \
work/includeModuleSV/.includeModuleSV_sv \
work/RTL_SVPackage/.RTL_SVPackage_sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo: ../../rtl/RTLTopModuleVerilogSimulationModel.vo
vlog -work work $(VLOG_FLAGS) +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl: ../../rtl/include/includeModuleBVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/genericTest/.genericTest_sv: src/genericTest.sv \
../sequences/sequence.sv \
../environment/Env_pkg.sv \
../environment/env.sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
../environment/top.sv \
src/FullTest_pkg.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../environment+../sequences+src +incdir+../../mvc//questa_mvc_src/sv+../../mvc/questa_mvc_src/sv/mvc_base+../../mvc/include+../../uvm-1.1d/src $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleVHDL/.includeModuleVHDL_vhdl: ../../rtl/include/includeModuleVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl: ../../rtl/include/includeModuleAVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl \
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl \
work/includeModuleVHDL/.includeModuleVHDL_vhdl \
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......
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