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Hdlmake
Commit db4e1ab6 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Dimitris Lampridis
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Prevent tool from compiling (system)verilog included files.

parent 943c08c5
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Showing with 21 additions and 7 deletions
hdlmake/srcfile.py
View file @ db4e1ab6
...@@ -42,6 +42,7 @@ class SourceFile(DepFile): ...@@ -42,6 +42,7 @@ class SourceFile(DepFile):
def __init__(self, path, module, library): def __init__(self, path, module, library):
assert isinstance(path, six.string_types) assert isinstance(path, six.string_types)
self.is_include = False
self.library = library self.library = library
if not library: if not library:
self.library = "work" self.library = "work"
...@@ -80,7 +81,7 @@ class VerilogFile(SourceFile): ...@@ -80,7 +81,7 @@ class VerilogFile(SourceFile):
"""This is the class providing the generic Verilog file""" """This is the class providing the generic Verilog file"""
def __init__(self, path, module, library=None, def __init__(self, path, module, library=None,
include_dirs=None): include_dirs=None, is_include=False):
SourceFile.__init__(self, path=path, module=module, library=library) SourceFile.__init__(self, path=path, module=module, library=library)
from hdlmake.vlog_parser import VerilogParser from hdlmake.vlog_parser import VerilogParser
self.include_dirs = [] self.include_dirs = []
...@@ -90,6 +91,7 @@ class VerilogFile(SourceFile): ...@@ -90,6 +91,7 @@ class VerilogFile(SourceFile):
self.parser = VerilogParser(self) self.parser = VerilogParser(self)
for dir_aux in self.include_paths: for dir_aux in self.include_paths:
self.parser.add_search_path(dir_aux) self.parser.add_search_path(dir_aux)
self.is_include = is_include
class SVFile(VerilogFile): class SVFile(VerilogFile):
...@@ -385,7 +387,7 @@ class SourceFileSet(set): ...@@ -385,7 +387,7 @@ class SourceFileSet(set):
def create_source_file(path, module, library=None, def create_source_file(path, module, library=None,
include_dirs=None): include_dirs=None, is_include=False):
"""Function that analyzes the given arguments and returns a new HDL source """Function that analyzes the given arguments and returns a new HDL source
file of the appropriated type""" file of the appropriated type"""
if path is None or path == "": if path is None or path == "":
...@@ -405,12 +407,14 @@ def create_source_file(path, module, library=None, ...@@ -405,12 +407,14 @@ def create_source_file(path, module, library=None,
new_file = VerilogFile(path=path, new_file = VerilogFile(path=path,
module=module, module=module,
library=library, library=library,
include_dirs=include_dirs) include_dirs=include_dirs,
is_include=is_include)
elif extension == 'sv' or extension == 'svh': elif extension == 'sv' or extension == 'svh':
new_file = SVFile(path=path, new_file = SVFile(path=path,
module=module, module=module,
library=library, library=library,
include_dirs=include_dirs) include_dirs=include_dirs,
is_include=is_include)
elif extension == 'wb': elif extension == 'wb':
new_file = WBGenFile(path=path, module=module) new_file = WBGenFile(path=path, module=module)
elif extension == 'tcl': elif extension == 'tcl':
......
hdlmake/tools/make_sim.py
View file @ db4e1ab6
...@@ -71,10 +71,13 @@ PWD := $$(shell pwd) ...@@ -71,10 +71,13 @@ PWD := $$(shell pwd)
fileset = self.fileset fileset = self.fileset
self.write("VERILOG_SRC := ") self.write("VERILOG_SRC := ")
for vlog in fileset.filter(VerilogFile): for vlog in fileset.filter(VerilogFile):
self.writeln(vlog.rel_path() + " \\") if not vlog.is_include:
self.writeln(vlog.rel_path() + " \\")
self.writeln() self.writeln()
self.write("VERILOG_OBJ := ") self.write("VERILOG_OBJ := ")
for vlog in fileset.filter(VerilogFile): for vlog in fileset.filter(VerilogFile):
if vlog.is_include:
continue
# make a file compilation indicator (these .dat files are made even # make a file compilation indicator (these .dat files are made even
# if the compilation process fails) and add an ending according # if the compilation process fails) and add an ending according
# to file's extension (.sv and .vhd files may have the same # to file's extension (.sv and .vhd files may have the same
...@@ -133,11 +136,15 @@ PWD := $$(shell pwd) ...@@ -133,11 +136,15 @@ PWD := $$(shell pwd)
# the file is included -> we depend directly on it # the file is included -> we depend directly on it
self.write(" \\\n" + dep_file.rel_path()) self.write(" \\\n" + dep_file.rel_path())
self.writeln() self.writeln()
is_include = False
if isinstance(file_aux, VHDLFile): if isinstance(file_aux, VHDLFile):
command_key = 'vhdl' command_key = 'vhdl'
elif (isinstance(file_aux, VerilogFile) or elif (isinstance(file_aux, VerilogFile) or
isinstance(file_aux, SVFile)): isinstance(file_aux, SVFile)):
is_include = file_aux.is_include
command_key = 'vlog' command_key = 'vlog'
if is_include:
continue
self.writeln("\t\t" + self._simulator_controls[command_key]) self.writeln("\t\t" + self._simulator_controls[command_key])
self.write("\t\t@" + shell.mkdir_command() + " $(dir $@)") self.write("\t\t@" + shell.mkdir_command() + " $(dir $@)")
self.writeln(" && " + shell.touch_command() + " $@ \n") self.writeln(" && " + shell.touch_command() + " $@ \n")
......
hdlmake/tools/sim_makefile_support.py
View file @ db4e1ab6
...@@ -130,6 +130,8 @@ class VsimMakefileWriter(ToolSim): ...@@ -130,6 +130,8 @@ class VsimMakefileWriter(ToolSim):
self.write('\n\n') self.write('\n\n')
# rules for all _primary.dat files for sv # rules for all _primary.dat files for sv
for vlog in fileset.filter(VerilogFile): for vlog in fileset.filter(VerilogFile):
if vlog.is_include:
continue
self.write("%s: %s" % (os.path.join( self.write("%s: %s" % (os.path.join(
vlog.library, vlog.purename, vlog.library, vlog.purename,
".%s_%s" % (vlog.purename, vlog.extension())), ".%s_%s" % (vlog.purename, vlog.extension())),
...@@ -137,7 +139,7 @@ class VsimMakefileWriter(ToolSim): ...@@ -137,7 +139,7 @@ class VsimMakefileWriter(ToolSim):
# list dependencies, do not include the target file # list dependencies, do not include the target file
for dep_file in [dfile for dfile for dep_file in [dfile for dfile
in vlog.depends_on if dfile is not vlog]: in vlog.depends_on if dfile is not vlog]:
if dep_file in fileset: if dep_file in fileset and not dep_file.is_include:
name = dep_file.purename name = dep_file.purename
extension = dep_file.extension() extension = dep_file.extension()
self.write(" \\\n" + os.path.join( self.write(" \\\n" + os.path.join(
......
hdlmake/vlog_parser.py
View file @ db4e1ab6
...@@ -583,7 +583,8 @@ class VerilogParser(DepParser): ...@@ -583,7 +583,8 @@ class VerilogParser(DepParser):
for file_aux in includes: for file_aux in includes:
dep_file.depends_on.add( dep_file.depends_on.add(
create_source_file(path=file_aux, create_source_file(path=file_aux,
module=dep_file.module)) module=dep_file.module,
is_include=True))
logging.debug("%s has %d includes.", logging.debug("%s has %d includes.",
str(dep_file), len(includes)) str(dep_file), len(includes))
except KeyError: except KeyError:
......
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