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Hdlmake
Commit ddae95d9 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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PEP8 auditing: fix 'hdlmake/tools/*'

parent 468b2ef2
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Showing with 20 additions and 18 deletions
hdlmake/tools/ghdl.py
View file @ ddae95d9
......@@ -74,4 +74,3 @@ class ToolGHDL(ToolSim):
self.writeln("\t\t" + self._simulator_controls['compiler'])
self.writeln('\n')
self.makefile_sim_dep_files()
hdlmake/tools/ise.py
View file @ ddae95d9
......@@ -60,7 +60,6 @@ class ToolISE(ToolSyn):
STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std',
'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib']
SUPPORTED_FILES = [UCFFile, CDCFile, NGCFile]
HDL_FILES = [VHDLFile, VerilogFile, SVFile]
......@@ -71,8 +70,9 @@ class ToolISE(ToolSyn):
"*.ngc", "*.ngd", "*.ngr", "*.pad", "*.par",
"*.pcf", "*.prj", "*.ptwx", "*.stx", "*.syr",
"*.twr", "*.twx", "*.gise", "*.gise", "*.bgn",
"*.unroutes", "*.ut", "*.xpi", "*.xst", "*.xise",
"*.xwbt", "*_envsettings.html", "*_guide.ncd",
"*.unroutes", "*.ut", "*.xpi", "*.xst",
"*.xise", "*.xwbt",
"*_envsettings.html", "*_guide.ncd",
"*_map.map", "*_map.mrp", "*_map.ncd",
"*_map.ngm", "*_map.xrpt", "*_ngdbuild.xrpt",
"*_pad.csv", "*_pad.txt", "*_par.xrpt",
......
hdlmake/tools/isim.py
View file @ ddae95d9
......@@ -68,6 +68,7 @@ class ToolISim(ToolSim):
def makefile_sim_top(self):
"""Print the top section of the Makefile for Xilinx ISim"""
top_module = self.top_module
def __get_xilinxsim_ini_dir(env):
"""Get Xilinx ISim ini simulation file"""
if env["isim_path"]:
......@@ -122,7 +123,7 @@ XILINX_INI_PATH := """ + __get_xilinxsim_ini_dir(top_module.pool.env) +
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ +
__get_rid_of_isim_incdirs(
self.top_module.manifest_dict["vlog_opt"]) + """
self.top_module.manifest_dict["vlog_opt"]) + """
""")
def makefile_sim_compilation(self):
......
hdlmake/tools/make_sim.py
View file @ ddae95d9
......@@ -7,6 +7,7 @@ from .makefile import ToolMakefile
from hdlmake.util import path as path_mod
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
class ToolSim(ToolMakefile):
"""Class that provides the Makefile writing methods and status"""
......
hdlmake/tools/make_syn.py
View file @ ddae95d9
......@@ -141,15 +141,19 @@ tcl_bitstream: tcl_par
run_tcl:
\t\t$(TCL_INTERPRETER)run.tcl
synthesize: tcl_clean tcl_open tcl_synthesize tcl_close syn_pre_synthesize_cmd run_tcl syn_post_synthesize_cmd
synthesize: tcl_clean tcl_open tcl_synthesize tcl_close \
syn_pre_synthesize_cmd run_tcl syn_post_synthesize_cmd
\t\ttouch $@ tcl_synthesize
translate: tcl_clean tcl_open tcl_translate tcl_close syn_pre_translate_cmd run_tcl syn_post_translate_cmd
translate: tcl_clean tcl_open tcl_translate tcl_close syn_pre_translate_cmd \
run_tcl syn_post_translate_cmd
\t\ttouch $@ tcl_translate tcl_synthesize
map: tcl_clean tcl_open tcl_map tcl_close syn_pre_map_cmd run_tcl syn_post_map_cmd
map: tcl_clean tcl_open tcl_map tcl_close syn_pre_map_cmd run_tcl \
syn_post_map_cmd
\t\ttouch $@ tcl_map tcl_translate tcl_synthesize
par: tcl_open tcl_par tcl_close syn_pre_par_cmd run_tcl syn_post_par_cmd
\t\ttouch $@ tcl_par tcl_map tcl_translate tcl_synthesize
bitstream: tcl_clean tcl_open tcl_bitstream tcl_close syn_pre_bitstream_cmd run_tcl syn_post_bitstream_cmd
bitstream: tcl_clean tcl_open tcl_bitstream tcl_close syn_pre_bitstream_cmd \
run_tcl syn_post_bitstream_cmd
\t\ttouch $@ tcl_bitstream tcl_par tcl_map tcl_translate tcl_synthesize
""")
......@@ -191,7 +195,7 @@ syn_post_bitstream_cmd:
""")
self.writeln(syn_command.substitute(
syn_pre_cmd=self.top_module.manifest_dict[
"syn_pre_cmd"],
"syn_pre_cmd"],
syn_post_cmd=self.top_module.manifest_dict[
"syn_post_cmd"],
syn_pre_synthesize_cmd=self.top_module.manifest_dict[
......
hdlmake/tools/quartus.py
View file @ ddae95d9
......@@ -29,8 +29,8 @@ import logging
from .make_syn import ToolSyn
from hdlmake.util import path as path_mod
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
SignalTapFile, SDCFile, QIPFile, QSYSFile, DPFFile,
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile,
SignalTapFile, SDCFile, QIPFile, QSYSFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile)
......@@ -176,7 +176,8 @@ class ToolQuartus(ToolSyn):
name=preflow))
if top_module.manifest_dict["quartus_postmodule"] is not None:
path = path_mod.compose(
top_module.manifest_dict["quartus_postmodule"], top_module.path)
top_module.manifest_dict["quartus_postmodule"],
top_module.path)
if not os.path.exists(path):
logging.error("quartus_postmodule file listed in "
+ top_module.path + " doesn't exist: "
......
hdlmake/tools/vivado.py
View file @ ddae95d9
......@@ -68,12 +68,9 @@ class ToolVivado(ToolXilinx, ToolSim):
self._tcl_controls.update(ToolVivado.TCL_CONTROLS)
self._simulator_controls.update(ToolVivado.SIMULATOR_CONTROLS)
def makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for Vivado Simulator"""
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + ToolVivado.SIMULATOR_CONTROLS['compiler'])
self.writeln()
self.makefile_sim_dep_files()
hdlmake/tools/writer.py
View file @ ddae95d9
......@@ -22,6 +22,7 @@ class WriterSim(object):
self.ghdl = ToolGHDL()
self.vivado = ToolVivado()
class WriterSyn(object):
"""Class that is in charge of writing synthesis Makefiles"""
......@@ -33,5 +34,3 @@ class WriterSyn(object):
self.quartus = ToolQuartus()
self.diamond = ToolDiamond()
self.libero = ToolLibero()
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