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Commit e42a630a authored by Adrian Fiergolski's avatar Adrian Fiergolski
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Fix test for bug 1028. 

Add logs for found primitives in vlog_parser.
parent b7f4c066
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Showing with 14 additions and 17 deletions
hdlmake/vhdl_parser.py
View file @ e42a630a
......@@ -130,15 +130,10 @@ class VHDLParser(DepParser):
what, g = matches[0]
if(what == "use"):
logging.debug("use package %s" % g.group(1)+"."+g.group(2) )
dep_file.add_relation(DepRelation(g.group(1)+"."+g.group(2), DepRelation.USE, DepRelation.PACKAGE))
if(what == "package"):
dep_file.add_relation(DepRelation(g.group(1),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(1)),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
elif(what == "entity"):
logging.debug("found entity %s" %g.group(1))
dep_file.add_relation(DepRelation(g.group(1),
DepRelation.PROVIDE,
DepRelation.ENTITY))
......@@ -146,6 +141,7 @@ class VHDLParser(DepParser):
DepRelation.PROVIDE,
DepRelation.ENTITY))
elif(what == "package"):
logging.debug("found package %s" %g.group(1))
dep_file.add_relation(DepRelation(g.group(1),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
......@@ -157,11 +153,10 @@ class VHDLParser(DepParser):
within_architecture = True
elif(what == "arch_end" and within_architecture and g.group(1) == arch_name):
within_architecture = False
elif(what == "instance" and within_architecture):
dep_file.add_relation(DepRelation(g.group(2),
DepRelation.USE,
DepRelation.ENTITY))
elif(what == "instance_from_work_library" and within_architecture) :
elif( what in ["instance", "instance_from_work_library"] and within_architecture):
logging.debug("-> instantiates %s as %s" % (g.group(1), g.group(2)) )
if (what == "instance_from_work_library") :
logging.info("Mam cie !!!!!!!!!!!!!!!!!!!! %s" % g.group(2) )
dep_file.add_relation(DepRelation(g.group(2),
DepRelation.USE,
DepRelation.ENTITY))
......
tests/questa_uvm_sv/rtl/RTLTopModuleVHDL.vhdl
View file @ e42a630a
......@@ -23,7 +23,7 @@ library ieee;
use ieee.std_logic_1164.all;
entity RTLTopModuleVHDL is
port ();
end entity RTLTopModuleVHDL;
architecture Behavioral of RTLTopModuleVHDL is
......
tests/questa_uvm_sv/rtl/include/includeModuleAVHDL.vhdl
View file @ e42a630a
......@@ -23,7 +23,7 @@ library ieee;
use ieee.std_logic_1164.all;
entity includeModuleAVHDL is
port ();
end entity includeModuleAVHDL;
architecture Behavioral of includeModuleAVHDL is
......
tests/questa_uvm_sv/rtl/include/includeModuleBVHDL.vhdl
View file @ e42a630a
......@@ -23,7 +23,7 @@ library ieee;
use ieee.std_logic_1164.all;
entity includeModuleBVHDL is
port();
end entity includeModuleBVHDL;
architecture Behavioral of includeModuleBVHDL is
......
tests/questa_uvm_sv/rtl/include/includeModuleVHDL.vhdl
View file @ e42a630a
......@@ -23,7 +23,7 @@ library ieee;
use ieee.std_logic_1164.all;
entity includeModuleVHDL is
port();
end entity includeModuleVHDL;
architecture Behavioral of includeModuleVHDL is
......
tests/questa_uvm_sv/sim/tests/Makefile
View file @ e42a630a
......@@ -113,7 +113,9 @@ work/includeModuleBVHDL/.includeModuleBVHDL_vhdl: ../../rtl/include/includeModul
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl \
work/includeModuleVHDL/.includeModuleVHDL_vhdl \
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......
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