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Hdlmake
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e66072bf
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e66072bf
authored
May 26, 2017
by
Javier D. Garcia-Lasheras
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Fix synthesis variables table in the documentation
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7a70c6ce
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docs/index.rst
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e66072bf
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@@ -1395,43 +1395,43 @@ Synthesis variables
Basic synthesis variables:
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+=================+=============+=================================================================+===========+
| syn_top | str | Top level module for synthesis | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_tool | str | Tool to be used in the synthesis | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_device | str | Target FPGA device | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_family | str | Target FPGA family | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_grade | str | Speed grade of target FPGA | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_package | str | Package variant of target FPGA | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_project | str | Project file name | None |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
| syn_pre_synthesize_cmd | str
| Command to be executed before synthesis: synthesize | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
| syn_post_synthesize_cmd | str
| Command to be executed after synthesis: synthesize | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
| syn_pre_translate_cmd | str
| Command to be executed before synthesis: translate | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
| syn_post_translate_cmd | str
| Command to be executed after synthesis: translate | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
| syn_pre_map_cmd | str
| Command to be executed before synthesis: map | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
| syn_post_map_cmd | str
| Command to be executed after synthesis: map | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
| syn_pre_par_cmd | str
| Command to be executed before synthesis: par | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
| syn_post_par_cmd | str
| Command to be executed after synthesis: par | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
| syn_pre_bitstream_cmd | str
| Command to be executed before synthesis: bitstream | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
| syn_post_bitstream_cmd | str
| Command to be executed after synthesis: bitstream | '' |
+--------------------------+-------------
-
+-----------------------------------------------------------------+-----------+
+-----------------
---------
+-------------+-----------------------------------------------------------------+-----------+
| Name
| Type | Description | Default |
+=================
=========
+=============+=================================================================+===========+
| syn_top
| str | Top level module for synthesis | None |
+-----------------
---------
+-------------+-----------------------------------------------------------------+-----------+
| syn_tool
| str | Tool to be used in the synthesis | None |
+-----------------
---------
+-------------+-----------------------------------------------------------------+-----------+
| syn_device
| str | Target FPGA device | None |
+-----------------
---------
+-------------+-----------------------------------------------------------------+-----------+
| syn_family
| str | Target FPGA family | None |
+-----------------
---------
+-------------+-----------------------------------------------------------------+-----------+
| syn_grade
| str | Speed grade of target FPGA | None |
+-----------------
---------
+-------------+-----------------------------------------------------------------+-----------+
| syn_package
| str | Package variant of target FPGA | None |
+-----------------
---------
+-------------+-----------------------------------------------------------------+-----------+
| syn_project
| str | Project file name | None |
+-----------------
---------
+-------------+-----------------------------------------------------------------+-----------+
| syn_pre_synthesize_cmd | str | Command to be executed before synthesis: synthesize | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_post_synthesize_cmd | str | Command to be executed after synthesis: synthesize | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_pre_translate_cmd | str | Command to be executed before synthesis: translate | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_post_translate_cmd | str | Command to be executed after synthesis: translate | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_pre_map_cmd | str | Command to be executed before synthesis: map | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_post_map_cmd | str | Command to be executed after synthesis: map | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_pre_par_cmd | str | Command to be executed before synthesis: par | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_post_par_cmd | str | Command to be executed after synthesis: par | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_pre_bitstream_cmd | str | Command to be executed before synthesis: bitstream | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_post_bitstream_cmd | str | Command to be executed after synthesis: bitstream | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
Altera Quartus II / Prime specific variables:
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