Recognise entire VHDL functions and entity instanciations as instances.

Gobble entire VHDL function to avoid input parameters being recognised as instances. Entity instanciations recognised as instances as well - borrowed from rjen's commit d0ba0268 on feat_svn_ise branch.

Recognise entire VHDL functions and entity instanciations as instances.
Gobble entire VHDL function to avoid input parameters being recognised as instances. Entity instanciations recognised as instances as well - borrowed from rjen's commit d0ba0268 on feat_svn_ise branch.
e8c1f12c · Will Kamp · 40d23369 · e8c1f12c
Commit e8c1f12c authored Feb 12, 2018 by Will Kamp
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Showing with 6 additions and 3 deletions

vhdl_parser.py hdlmake/vhdl_parser.py +6 -3

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--- a/hdlmake/vhdl_parser.py
+++ b/hdlmake/vhdl_parser.py
@@ -227,7 +227,11 @@ class VHDLParser(DepParser):
        # function declaration
        function_pattern = re.compile(
-            r"^\s*function\s+(?P<name>\w+)",
+            r"^\s*function\s+(?P<name>\w+)"
+            r".*?" # gobble arguments if any.
+            r"return\s+\w+"
+            r"(\s+is.*?end\s+function.*?)?" # gobble body if any.
+            r"\s*;",
            re.DOTALL | re.MULTILINE | re.IGNORECASE)
        def do_function(text):
@@ -243,8 +247,7 @@ class VHDLParser(DepParser):
        # instantions
        libraries = set([dep_file.library])
        instance_pattern = re.compile(
-            r"^\s*(\w+)\s*\:\s*(\w+)\s*(?:port\s+map.*?;"
+            r"^\s*(\w+)\s*:\s*(?:entity\s+\w+\.)?(\w+)\s*(?:port\s+map.*?|generic\s+map.*?)",
-            r"|generic\s+map.*?;|\s*;)",
            re.DOTALL | re.MULTILINE | re.IGNORECASE)
        def do_instance(text):