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Hdlmake
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e8d09edb
Commit
e8d09edb
authored
Feb 07, 2015
by
Garcia-Lasheras
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Add IVerilog VHDL based counter test
parent
6d4d3661
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Manifest.py
tests/counter/sim/iverilog/vhdl/Manifest.py
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tests/counter/sim/iverilog/vhdl/Manifest.py
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e8d09edb
action
=
"simulation"
sim_tool
=
"iverilog"
top_module
=
"counter_tb"
sim_pre_cmd
=
"echo IMPORTANT, IVerilog always needs a Verilog testbench, no matter if the DUT is written in VHDL!"
sim_post_cmd
=
"vvp counter_tb.vvp; gtkwave counter_tb.vcd"
files
=
[
"../../../modules/counter/vhdl/counter.vhd"
,
"../../../testbench/counter_tb/verilog/counter_tb.v"
,
]
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