Skip to content

H
Hdlmake
Commit ec286e54 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
Browse files
Options

Refactor makefile writing functions into syn/sim specific Classes

parent 405801c4
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 359 additions and 325 deletions
hdlmake/action/makefile.py
View file @ ec286e54
This diff is collapsed.
hdlmake/tools/__init__.py
View file @ ec286e54
......@@ -6,6 +6,8 @@ from .riviera import ToolRiviera
from .ghdl import ToolGHDL
from .sim_makefile_support import VsimMakefileWriter
from .make_syn import ToolSyn
from .make_sim import ToolSim
from .xilinx import ToolXilinx
from .ise import ToolISE
from .planahead import ToolPlanAhead
......
hdlmake/tools/active_hdl.py
View file @ ec286e54
......@@ -23,11 +23,11 @@
"""Module providing support for Aldec Active-HDL simulator"""
from hdlmake.action import ActionMakefile
from .make_sim import ToolSim
from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile
class ToolActiveHDL(ActionMakefile):
class ToolActiveHDL(ToolSim):
"""Class providing the interface to control an Active-HDL simulation"""
......
hdlmake/tools/diamond.py
View file @ ec286e54
......@@ -24,13 +24,13 @@
"""Module providing support for Lattice Diamond IDE"""
from hdlmake.action import ActionMakefile
from .make_syn import ToolSyn
from hdlmake.srcfile import EDFFile, LPFFile
DIAMOND_STANDARD_LIBS = ['ieee', 'std']
class ToolDiamond(ActionMakefile):
class ToolDiamond(ToolSyn):
"""Class providing the interface for Lattice Diamond synthesis"""
......
hdlmake/tools/ghdl.py
View file @ ec286e54
......@@ -24,13 +24,14 @@
"""Module providing support for GHDL simulator"""
import string
from hdlmake.action import ActionMakefile
from .make_sim import ToolSim
from hdlmake.srcfile import VHDLFile
GHDL_STANDARD_LIBS = ['ieee', 'std']
class ToolGHDL(ActionMakefile):
class ToolGHDL(ToolSim):
"""Class providing the interface for Lattice Diamond synthesis"""
......
hdlmake/tools/ise.py
View file @ ec286e54
......@@ -30,7 +30,7 @@ import logging
import re
from subprocess import Popen, PIPE
from hdlmake.action import ActionMakefile
from .make_syn import ToolSyn
from hdlmake.util import path as path_mod
from hdlmake.srcfile import (UCFFile, CDCFile, NGCFile)
......@@ -52,7 +52,7 @@ ISE_STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std',
'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib']
class ToolISE(ActionMakefile):
class ToolISE(ToolSyn):
"""Class providing the methods to create and build a Xilinx ISE project"""
......
hdlmake/tools/isim.py
View file @ ec286e54
......@@ -32,7 +32,7 @@ import logging
import sys
from hdlmake.util import path as path_mod
from hdlmake.action import ActionMakefile
from .make_sim import ToolSim
from hdlmake.srcfile import VerilogFile, VHDLFile
......@@ -43,7 +43,7 @@ ISIM_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
class ToolISim(ActionMakefile):
class ToolISim(ToolSim):
"""Class providing the interface for Xilinx ISim simulator"""
......
hdlmake/tools/iverilog.py
View file @ ec286e54
......@@ -27,7 +27,7 @@ from subprocess import Popen, PIPE
import string
from hdlmake.util import path as path_mod
from hdlmake.action import ActionMakefile
from .make_sim import ToolSim
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
......@@ -38,7 +38,7 @@ IVERILOG_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
class ToolIVerilog(ActionMakefile):
class ToolIVerilog(ToolSim):
"""Class providing the interface for Icarus Verilog simulator"""
......
hdlmake/tools/libero.py
View file @ ec286e54
......@@ -24,14 +24,14 @@
"""Module providing support for Microsemi Libero IDE synthesis"""
from hdlmake.action import ActionMakefile
from .make_syn import ToolSyn
from hdlmake.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile
LIBERO_STANDARD_LIBS = ['ieee', 'std']
class ToolLibero(ActionMakefile):
class ToolLibero(ToolSyn):
"""Class providing the interface for Microsemi Libero IDE synthesis"""
......
hdlmake/tools/make_sim.py 0 → 100644
View file @ ec286e54
"""Module providing the synthesis functionality for writing Makefiles"""
import os
import sys
import string
import platform
from hdlmake.action import ActionMakefile
from hdlmake.util import path as path_mod
class ToolSim(ActionMakefile):
"""Class that provides the Makefile writing methods and status"""
def __init__(self):
super(ToolSim, self).__init__()
def makefile_sim_top(self, top_module):
top_parameter = string.Template("""\
TOP_MODULE := ${top_module}
PWD := $$(shell pwd)
""")
self.writeln(top_parameter.substitute(
top_module=top_module.manifest_dict["sim_top"]))
def makefile_sim_options(self, top_module):
pass
def makefile_sim_local(self, top_module):
self.writeln("#target for performing local simulation\n"
"local: sim_pre_cmd simulation sim_post_cmd\n")
def makefile_sim_sources(self, fileset):
from hdlmake.srcfile import VerilogFile, VHDLFile
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
self.write(vl.rel_path() + " \\\n")
self.write("\n")
self.write("VERILOG_OBJ := ")
for vl in fileset.filter(VerilogFile):
# make a file compilation indicator (these .dat files are made even if
# the compilation process fails) and add an ending according to file's
# extension (.sv and .vhd files may have the same corename and this
# causes a mess
self.write(
os.path.join(
vl.library,
vl.purename,
"." +
vl.purename +
"_" +
vl.extension(
)) +
" \\\n")
self.write('\n')
self.write("VHDL_SRC := ")
for vhdl in fileset.filter(VHDLFile):
self.write(vhdl.rel_path() + " \\\n")
self.writeln()
# list vhdl objects (_primary.dat files)
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile):
# file compilation indicator (important: add _vhd ending)
self.write(
os.path.join(
vhdl.library,
vhdl.purename,
"." +
vhdl.purename +
"_" +
vhdl.extension(
)) +
" \\\n")
self.write('\n')
def makefile_sim_command(self, top_module):
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
sim_command = string.Template("""# USER SIM COMMANDS
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd:
\t\t${sim_post_cmd}
""")
self.writeln(sim_command.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd))
def makefile_sim_clean(self, clean_targets):
"""Print the Makefile clean target for synthesis"""
self._print_tool_clean(clean_targets)
self._print_tool_mrproper(clean_targets)
def makefile_sim_phony(self, top_module):
"""Print simulation PHONY target list to the Makefile"""
self.writeln(
".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation")
hdlmake/tools/make_syn.py 0 → 100644
View file @ ec286e54
"""Module providing the synthesis functionality for writing Makefiles"""
import os
import sys
import string
import platform
from hdlmake.action import ActionMakefile
from hdlmake.util import path as path_mod
class ToolSyn(ActionMakefile):
"""Class that provides the Makefile writing methods and status"""
def __init__(self):
super(ToolSyn, self).__init__()
def makefile_syn_top(self, top_module, tool_path, tool_info):
"""Create the top part of the synthesis Makefile"""
if path_mod.check_windows():
tcl_interpreter = tool_info["windows_bin"]
else:
tcl_interpreter = tool_info["linux_bin"]
top_parameter = string.Template("""\
TOP_MODULE := ${top_module}
PWD := $$(shell pwd)
PROJECT := ${project_name}
PROJECT_FILE := $$(PROJECT).${project_ext}
TOOL_PATH := ${tool_path}
TCL_INTERPRETER := $$(TOOL_PATH)/${tcl_interpreter}
""")
self.writeln(top_parameter.substitute(
tcl_interpreter=tcl_interpreter,
project_name=top_module.manifest_dict["syn_project"],
project_ext=tool_info["project_ext"],
tool_path=tool_path,
top_module=top_module.manifest_dict["syn_top"]))
def makefile_syn_tcl(self, top_module, tcl_controls):
"""Create the Makefile TCL dictionary for the selected tool"""
tcl_string = string.Template("""\
define TCL_CREATE
${tcl_create}
endef
export TCL_CREATE
define TCL_OPEN
${tcl_open}
endef
export TCL_OPEN
define TCL_SAVE
${tcl_save}
endef
export TCL_SAVE
define TCL_CLOSE
${tcl_close}
endef
export TCL_CLOSE
define TCL_SYNTHESIZE
${tcl_synthesize}
endef
export TCL_SYNTHESIZE
define TCL_TRANSLATE
${tcl_translate}
endef
export TCL_TRANSLATE
define TCL_MAP
${tcl_map}
endef
export TCL_MAP
define TCL_PAR
${tcl_par}
endef
export TCL_PAR
define TCL_BITSTREAM
${tcl_bitstream}
endef
export TCL_BITSTREAM
""")
self.writeln(tcl_string.substitute(
tcl_create=tcl_controls["create"],
tcl_open=tcl_controls["open"],
tcl_save=tcl_controls["save"],
tcl_close=tcl_controls["close"],
tcl_synthesize=tcl_controls["synthesize"],
tcl_translate=tcl_controls["translate"],
tcl_map=tcl_controls["map"],
tcl_par=tcl_controls["par"],
tcl_bitstream=tcl_controls["bitstream"]))
def makefile_syn_local(self):
self.writeln("#target for performing local synthesis\n"
"local: syn_pre_cmd synthesis syn_post_cmd\n")
def makefile_syn_build(self):
"""Generate a Makefile to handle a synthesis project"""
self.writeln("""\
#target for performing local synthesis
synthesis: bitstream
tcl_clean:
\t\techo "" > run.tcl
ifeq ($(wildcard $(PROJECT_FILE)),)
tcl_open:
\t\t# The project doesn't exist, create
\t\techo "$$TCL_CREATE" >> run.tcl
\t\techo "$$TCL_FILES" >> run.tcl
else
tcl_open:
\t\t# The project exists, update
\t\techo "$$TCL_OPEN" >> run.tcl
endif
tcl_save:
\t\techo "$$TCL_SAVE" >> run.tcl
tcl_close: tcl_save
\t\techo "$$TCL_CLOSE" >> run.tcl
tcl_synthesize:
\t\techo "$$TCL_SYNTHESIZE" >> run.tcl
tcl_translate: tcl_synthesize
\t\techo "$$TCL_TRANSLATE" >> run.tcl
tcl_map: tcl_translate
\t\techo "$$TCL_MAP" >> run.tcl
tcl_par: tcl_map
\t\techo "$$TCL_PAR" >> run.tcl
tcl_bitstream: tcl_par
\t\techo "$$TCL_BITSTREAM" >> run.tcl
run_tcl:
\t\t$(TCL_INTERPRETER)run.tcl
synthesize: tcl_clean tcl_open tcl_synthesize tcl_close syn_pre_synthesize_cmd run_tcl syn_post_synthesize_cmd
\t\ttouch $@ tcl_synthesize
translate: tcl_clean tcl_open tcl_translate tcl_close syn_pre_translate_cmd run_tcl syn_post_translate_cmd
\t\ttouch $@ tcl_translate tcl_synthesize
map: tcl_clean tcl_open tcl_map tcl_close syn_pre_map_cmd run_tcl syn_post_map_cmd
\t\ttouch $@ tcl_map tcl_translate tcl_synthesize
par: tcl_open tcl_par tcl_close syn_pre_par_cmd run_tcl syn_post_par_cmd
\t\ttouch $@ tcl_par tcl_map tcl_translate tcl_synthesize
bitstream: tcl_clean tcl_open tcl_bitstream tcl_close syn_pre_bitstream_cmd run_tcl syn_post_bitstream_cmd
\t\ttouch $@ tcl_bitstream tcl_par tcl_map tcl_translate tcl_synthesize
""")
def makefile_syn_command(self, top_module):
"""Create the Makefile targets for user defined commands"""
syn_command = string.Template("""\
# User defined commands
syn_pre_cmd:
\t\t${syn_pre_cmd}
syn_post_cmd:
\t\t${syn_post_cmd}
syn_pre_synthesize_cmd:
\t\t${syn_pre_synthesize_cmd}
syn_post_synthesize_cmd:
\t\t${syn_post_synthesize_cmd}
syn_pre_translate_cmd:
\t\t${syn_pre_translate_cmd}
syn_post_translate_cmd:
\t\t${syn_post_translate_cmd}
syn_pre_map_cmd:
\t\t${syn_pre_map_cmd}
syn_post_map_cmd:
\t\t${syn_post_map_cmd}
syn_pre_par_cmd:
\t\t${syn_pre_par_cmd}
syn_post_par_cmd:
\t\t${syn_post_par_cmd}
syn_pre_bitstream_cmd:
\t\t${syn_pre_bitstream_cmd}
syn_post_bitstream_cmd:
\t\t${syn_post_bitstream_cmd}
""")
self.writeln(syn_command.substitute(
syn_pre_cmd=top_module.manifest_dict[
"syn_pre_cmd"],
syn_post_cmd=top_module.manifest_dict[
"syn_post_cmd"],
syn_pre_synthesize_cmd=top_module.manifest_dict[
"syn_pre_synthesize_cmd"],
syn_post_synthesize_cmd=top_module.manifest_dict[
"syn_post_synthesize_cmd"],
syn_pre_translate_cmd=top_module.manifest_dict[
"syn_pre_translate_cmd"],
syn_post_translate_cmd=top_module.manifest_dict[
"syn_post_translate_cmd"],
syn_pre_map_cmd=top_module.manifest_dict[
"syn_pre_map_cmd"],
syn_post_map_cmd=top_module.manifest_dict[
"syn_post_map_cmd"],
syn_pre_par_cmd=top_module.manifest_dict[
"syn_pre_par_cmd"],
syn_post_par_cmd=top_module.manifest_dict[
"syn_post_par_cmd"],
syn_pre_bitstream_cmd=top_module.manifest_dict[
"syn_pre_bitstream_cmd"],
syn_post_bitstream_cmd=top_module.manifest_dict[
"syn_post_bitstream_cmd"]))
def makefile_syn_clean(self, clean_targets):
"""Print the Makefile clean target for synthesis"""
self._print_tool_clean(clean_targets)
self.writeln("\t\t" + path_mod.del_command() +
" synthesize translate map par bitstream")
self.writeln("\t\t" + path_mod.del_command() +
" tcl_synthesize tcl_translate tcl_map tcl_par tcl_bitstream")
self._print_tool_mrproper(clean_targets)
def makefile_syn_phony(self):
"""Print synthesis PHONY target list to the Makefile"""
self.writeln(
".PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis")
hdlmake/tools/quartus.py
View file @ ec286e54
......@@ -27,7 +27,7 @@ import os
import sys
import logging
from hdlmake.action import ActionMakefile
from .make_syn import ToolSyn
from hdlmake.util import path as path_mod
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
SignalTapFile, SDCFile, QIPFile, QSYSFile, DPFFile,
......@@ -37,7 +37,7 @@ from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
QUARTUS_STANDARD_LIBS = ['altera', 'altera_mf', 'lpm', 'ieee', 'std']
class ToolQuartus(ActionMakefile):
class ToolQuartus(ToolSyn):
"""Class providing the interface for Altera Quartus synthesis"""
......
hdlmake/tools/sim_makefile_support.py
View file @ ec286e54
......@@ -27,11 +27,11 @@ import os
import platform
import string
from hdlmake.action import ActionMakefile
from .make_sim import ToolSim
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
class VsimMakefileWriter(ActionMakefile):
class VsimMakefileWriter(ToolSim):
"""A Makefile writer for simulation suitable for vsim based simulators.
......
hdlmake/tools/xilinx.py
View file @ ec286e54
......@@ -29,7 +29,7 @@ import os
import string
import logging
from hdlmake.action import ActionMakefile
from .make_syn import ToolSyn
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, UCFFile,
NGCFile, XMPFile, XCOFile, BDFile, TCLFile)
......@@ -37,7 +37,7 @@ from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, UCFFile,
VIVADO_STANDARD_LIBS = ['ieee', 'std']
class ToolXilinx(ActionMakefile):
class ToolXilinx(ToolSyn):
"""Class providing the interface for Xilinx Vivado synthesis"""
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment