Commit f38d03cd authored by Adrian Fiergolski's avatar Adrian Fiergolski

Fix bug 1761: VHDL instantiations with archietecture selection

parent 1a5fc8ee
......@@ -248,7 +248,7 @@ class VHDLParser(DepParser):
# instantions
libraries = set([dep_file.library])
instance_pattern = re.compile(
r"^\s*(\w+)\s*:\s*(?:entity\s+\w+\.)?(\w+)\s*(?:port\s+map.*?|generic\s+map.*?)",
r"^\s*(\w+)\s*:\s*(?:entity\s+\w+\.)?(\w+)\s*(?:\(\s*\w+\s*\)\s*)?(?:port\s+map.*?|generic\s+map.*?)",
re.DOTALL | re.MULTILINE | re.IGNORECASE)
def do_instance(text):
......
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