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Hdlmake
Commits
f394aafd
Commit
f394aafd
authored
Feb 05, 2018
by
Tomasz Wlostowski
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modelsim: don't compile included files. Hacking vivado-sim support
parent
a6fb09a7
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6 changed files
with
52 additions
and
25 deletions
+52
-25
__main__.py
hdlmake/__main__.py
+0
-0
srcfile.py
hdlmake/srcfile.py
+8
-4
make_sim.py
hdlmake/tools/make_sim.py
+23
-15
sim_makefile_support.py
hdlmake/tools/sim_makefile_support.py
+11
-2
vivado_sim.py
hdlmake/tools/vivado_sim.py
+8
-3
vlog_parser.py
hdlmake/vlog_parser.py
+2
-1
No files found.
hdlmake/__main__.py
100644 → 100755
View file @
f394aafd
File mode changed from 100644 to 100755
hdlmake/srcfile.py
View file @
f394aafd
...
...
@@ -42,6 +42,7 @@ class SourceFile(DepFile):
def
__init__
(
self
,
path
,
module
,
library
):
assert
isinstance
(
path
,
six
.
string_types
)
self
.
is_include
=
False
self
.
library
=
library
if
not
library
:
self
.
library
=
"work"
...
...
@@ -80,7 +81,7 @@ class VerilogFile(SourceFile):
"""This is the class providing the generic Verilog file"""
def
__init__
(
self
,
path
,
module
,
library
=
None
,
include_dirs
=
None
):
include_dirs
=
None
,
is_include
=
False
):
SourceFile
.
__init__
(
self
,
path
=
path
,
module
=
module
,
library
=
library
)
from
hdlmake.vlog_parser
import
VerilogParser
self
.
include_dirs
=
[]
...
...
@@ -90,6 +91,7 @@ class VerilogFile(SourceFile):
self
.
parser
=
VerilogParser
(
self
)
for
dir_aux
in
self
.
include_paths
:
self
.
parser
.
add_search_path
(
dir_aux
)
self
.
is_include
=
is_include
class
SVFile
(
VerilogFile
):
...
...
@@ -379,7 +381,7 @@ class SourceFileSet(set):
def
create_source_file
(
path
,
module
,
library
=
None
,
include_dirs
=
None
):
include_dirs
=
None
,
is_include
=
False
):
"""Function that analyzes the given arguments and returns a new HDL source
file of the appropriated type"""
if
path
is
None
or
path
==
""
:
...
...
@@ -399,12 +401,14 @@ def create_source_file(path, module, library=None,
new_file
=
VerilogFile
(
path
=
path
,
module
=
module
,
library
=
library
,
include_dirs
=
include_dirs
)
include_dirs
=
include_dirs
,
is_include
=
is_include
)
elif
extension
==
'sv'
or
extension
==
'svh'
:
new_file
=
SVFile
(
path
=
path
,
module
=
module
,
library
=
library
,
include_dirs
=
include_dirs
)
include_dirs
=
include_dirs
,
is_include
=
is_include
)
elif
extension
==
'wb'
:
new_file
=
WBGenFile
(
path
=
path
,
module
=
module
)
elif
extension
==
'tcl'
:
...
...
hdlmake/tools/make_sim.py
View file @
f394aafd
...
...
@@ -71,24 +71,27 @@ PWD := $$(shell pwd)
fileset
=
self
.
fileset
self
.
write
(
"VERILOG_SRC := "
)
for
vlog
in
fileset
.
filter
(
VerilogFile
):
self
.
writeln
(
vlog
.
rel_path
()
+
"
\\
"
)
if
not
vlog
.
is_include
:
self
.
writeln
(
vlog
.
rel_path
()
+
"
\\
"
)
self
.
writeln
()
self
.
write
(
"VERILOG_OBJ := "
)
for
vlog
in
fileset
.
filter
(
VerilogFile
):
if
not
vlog
.
is_include
:
# make a file compilation indicator (these .dat files are made even
# if the compilation process fails) and add an ending according
# to file's extension (.sv and .vhd files may have the same
# corename and this causes a mess
self
.
writeln
(
os
.
path
.
join
(
vlog
.
library
,
vlog
.
purename
,
"."
+
vlog
.
purename
+
"_"
+
vlog
.
extension
(
))
+
"
\\
"
)
self
.
writeln
(
os
.
path
.
join
(
vlog
.
library
,
vlog
.
purename
,
"."
+
vlog
.
purename
+
"_"
+
vlog
.
extension
(
))
+
"
\\
"
)
self
.
writeln
()
self
.
write
(
"VHDL_SRC := "
)
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
...
...
@@ -133,15 +136,20 @@ PWD := $$(shell pwd)
# the file is included -> we depend directly on it
self
.
write
(
"
\\\n
"
+
dep_file
.
rel_path
())
self
.
writeln
()
is_include
=
False
if
isinstance
(
file_aux
,
VHDLFile
):
command_key
=
'vhdl'
aux_opts
=
""
elif
(
isinstance
(
file_aux
,
VerilogFile
)
or
isinstance
(
file_aux
,
SVFile
)):
is_include
=
file_aux
.
is_include
command_key
=
'vlog'
self
.
writeln
(
"
\t\t
"
+
self
.
_simulator_controls
[
command_key
])
self
.
write
(
"
\t\t
@"
+
shell
.
mkdir_command
()
+
" $(dir $@)"
)
self
.
writeln
(
" && "
+
shell
.
touch_command
()
+
" $@
\n
"
)
self
.
writeln
()
aux_opts
=
""
if
not
is_include
:
self
.
writeln
(
"
\t\t
"
+
self
.
_simulator_controls
[
command_key
]
+
" "
+
aux_opts
)
self
.
write
(
"
\t\t
@"
+
shell
.
mkdir_command
()
+
" $(dir $@)"
)
self
.
writeln
(
" && "
+
shell
.
touch_command
()
+
" $@
\n
"
)
self
.
writeln
()
def
_makefile_sim_command
(
self
):
"""Generic method to write the simulation Makefile user commands"""
...
...
hdlmake/tools/sim_makefile_support.py
View file @
f394aafd
...
...
@@ -127,6 +127,8 @@ class VsimMakefileWriter(ToolSim):
self
.
write
(
'
\n\n
'
)
# rules for all _primary.dat files for sv
for
vlog
in
fileset
.
filter
(
VerilogFile
):
if
vlog
.
is_include
:
continue
self
.
write
(
"
%
s:
%
s"
%
(
os
.
path
.
join
(
vlog
.
library
,
vlog
.
purename
,
".
%
s_
%
s"
%
(
vlog
.
purename
,
vlog
.
extension
())),
...
...
@@ -134,7 +136,7 @@ class VsimMakefileWriter(ToolSim):
# list dependencies, do not include the target file
for
dep_file
in
[
dfile
for
dfile
in
vlog
.
depends_on
if
dfile
is
not
vlog
]:
if
dep_file
in
fileset
:
if
not
dep_file
.
is_include
:
#
in fileset:
name
=
dep_file
.
purename
extension
=
dep_file
.
extension
()
self
.
write
(
"
\\\n
"
+
os
.
path
.
join
(
...
...
@@ -142,8 +144,15 @@ class VsimMakefileWriter(ToolSim):
else
:
# the file is included -> we depend directly on the file
self
.
write
(
"
\\\n
"
+
dep_file
.
rel_path
())
self
.
writeln
()
aux_opts
=
""
for
inc
in
vlog
.
include_dirs
:
print
(
"DO INCLUDE"
,
inc
)
aux_opts
+=
"+incdir+"
+
inc
+
" "
compile_template
=
string
.
Template
(
"
\t\t
vlog -work ${library} $$(VLOG_FLAGS) "
"
\t\t
vlog -work ${library} $$(VLOG_FLAGS) "
+
aux_opts
+
"${sv_option} $${INCLUDE_DIRS} $$<"
)
compile_line
=
compile_template
.
substitute
(
library
=
vlog
.
library
,
sv_option
=
"-sv"
...
...
hdlmake/tools/vivado_sim.py
View file @
f394aafd
...
...
@@ -47,9 +47,10 @@ class ToolVivadoSim(ToolSim):
"work"
,
"xsim.dir"
],
'mrproper'
:
[
"*.wdb"
,
"*.vcd"
]}
SIMULATOR_CONTROLS
=
{
'vlog'
:
'xvlog $<'
,
'vhdl'
:
'xvhdl $<'
,
'compiler'
:
'xelab -debug all $(TOP_MODULE) '
SIMULATOR_CONTROLS
=
{
'vlog'
:
'$(eval vlog_srcs := $(vlog_srcs) $^)'
,
'vhdl'
:
'$(eval vhdl_srcs := $(vhdl_srcs) $^)'
,
'compiler'
:
'xvhdl $(XVHDL_OPT) $(vhdl_srcs); xvlog $(XVLOG_OPT) $(vlog_srcs); xelab -debug all $(XELAB_OPT) $(TOP_MODULE) '
'-s $(TOP_MODULE)'
}
def
__init__
(
self
):
...
...
@@ -62,6 +63,10 @@ class ToolVivadoSim(ToolSim):
def
_makefile_sim_compilation
(
self
):
"""Generate compile simulation Makefile target for Vivado Simulator"""
self
.
writeln
(
"XVLOG_OPT :=
%
s"
%
self
.
manifest_dict
.
get
(
"vlog_opt"
,
''
))
self
.
writeln
(
"XVHDL_OPT :=
%
s"
%
self
.
manifest_dict
.
get
(
"vcom_opt"
,
''
))
self
.
writeln
(
"XELAB_OPT := "
)
self
.
writeln
(
"simulation: $(VERILOG_OBJ) $(VHDL_OBJ)"
)
self
.
writeln
(
"
\t\t
"
+
ToolVivadoSim
.
SIMULATOR_CONTROLS
[
'compiler'
])
self
.
writeln
()
...
...
hdlmake/vlog_parser.py
View file @
f394aafd
...
...
@@ -582,7 +582,8 @@ class VerilogParser(DepParser):
for
file_aux
in
includes
:
dep_file
.
depends_on
.
add
(
create_source_file
(
path
=
file_aux
,
module
=
dep_file
.
module
))
module
=
dep_file
.
module
,
is_include
=
True
))
logging
.
debug
(
"
%
s has
%
d includes."
,
str
(
dep_file
),
len
(
includes
))
except
KeyError
:
...
...
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