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Commit f5fd4714 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Split Vivado into two different tool modules for synthesis and simulation

parent 9d5ff18d
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Showing with 75 additions and 22 deletions
hdlmake/tools/makefile_writer.py
View file @ f5fd4714
......@@ -37,14 +37,14 @@ def load_sim_tool(tool_name):
from .active_hdl import ToolActiveHDL
from .riviera import ToolRiviera
from .ghdl import ToolGHDL
from .vivado import ToolVivado
from .vivado_sim import ToolVivadoSim
available_tools = {'iverilog': ToolIVerilog,
'isim': ToolISim,
'modelsim': ToolModelsim,
'active_hdl': ToolActiveHDL,
'riviera': ToolRiviera,
'ghdl': ToolGHDL,
'vivado': ToolVivado}
'vivado_sim': ToolVivadoSim}
if tool_name in available_tools:
logging.debug("Simulation tool to be used found: %s", tool_name)
return available_tools[tool_name]()
......
hdlmake/tools/vivado.py
View file @ f5fd4714
......@@ -26,13 +26,12 @@
from __future__ import absolute_import
from .xilinx import ToolXilinx
from .make_sim import ToolSim
from hdlmake.srcfile import (XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, COEFile, BDFile, TCLFile,
MIFFile, RAMFile, VHOFile, VEOFile)
class ToolVivado(ToolXilinx, ToolSim):
class ToolVivado(ToolXilinx):
"""Class providing the interface for Xilinx Vivado synthesis"""
......@@ -62,9 +61,8 @@ class ToolVivado(ToolXilinx, ToolSim):
CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", "*.pb",
"$(PROJECT).cache", "$(PROJECT).data", "work",
"$(PROJECT).runs", "$(PROJECT).hw", "xsim.dir",
"$(PROJECT).ip_user_files", "$(PROJECT_FILE)"],
'mrproper': ["*.wdb", "*.vcd"]}
"$(PROJECT).runs", "$(PROJECT).hw",
"$(PROJECT).ip_user_files", "$(PROJECT_FILE)"]}
TCL_CONTROLS = {'bitstream': '$(TCL_OPEN)\n'
'launch_runs impl_1 -to_step write_bitstream'
......@@ -72,11 +70,6 @@ class ToolVivado(ToolXilinx, ToolSim):
'wait_on_run impl_1\n'
'$(TCL_CLOSE)'}
SIMULATOR_CONTROLS = {'vlog': 'xvlog $<',
'vhdl': 'xvhdl $<',
'compiler': 'xelab -debug all $(TOP_MODULE) '
'-s $(TOP_MODULE)'}
def __init__(self):
super(ToolVivado, self).__init__()
self._tool_info.update(ToolVivado.TOOL_INFO)
......@@ -84,11 +77,3 @@ class ToolVivado(ToolXilinx, ToolSim):
self._standard_libs.extend(ToolVivado.STANDARD_LIBS)
self._clean_targets.update(ToolVivado.CLEAN_TARGETS)
self._tcl_controls.update(ToolVivado.TCL_CONTROLS)
self._simulator_controls.update(ToolVivado.SIMULATOR_CONTROLS)
def _makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for Vivado Simulator"""
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + ToolVivado.SIMULATOR_CONTROLS['compiler'])
self.writeln()
self._makefile_sim_dep_files()
hdlmake/tools/vivado_sim.py 0 → 100644
View file @ f5fd4714
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for Xilinx Vivado simulation"""
from __future__ import absolute_import
from .make_sim import ToolSim
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
class ToolVivadoSim(ToolSim):
"""Class providing the interface for Xilinx Vivado synthesis"""
TOOL_INFO = {
'name': 'vivado-sim',
'id': 'vivado-sim',
'windows_bin': 'vivado.exe -mode tcl -source',
'linux_bin': 'vivado -mode tcl -source',
}
STANDARD_LIBS = ['ieee', 'std']
HDL_FILES = {VerilogFile: '', VHDLFile: '', SVFile: ''}
CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", "*.pb",
"work", "xsim.dir"],
'mrproper': ["*.wdb", "*.vcd"]}
SIMULATOR_CONTROLS = {'vlog': 'xvlog $<',
'vhdl': 'xvhdl $<',
'compiler': 'xelab -debug all $(TOP_MODULE) '
'-s $(TOP_MODULE)'}
def __init__(self):
super(ToolVivadoSim, self).__init__()
self._tool_info.update(ToolVivadoSim.TOOL_INFO)
self._standard_libs.extend(ToolVivadoSim.STANDARD_LIBS)
self._clean_targets.update(ToolVivadoSim.CLEAN_TARGETS)
self._simulator_controls.update(ToolVivadoSim.SIMULATOR_CONTROLS)
self._hdl_files.update(ToolVivadoSim.HDL_FILES)
def _makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for Vivado Simulator"""
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + ToolVivadoSim.SIMULATOR_CONTROLS['compiler'])
self.writeln()
self._makefile_sim_dep_files()
tests/counter/sim/vivado/verilog/Manifest.py
View file @ f5fd4714
action = "simulation"
sim_tool = "vivado"
sim_tool = "vivado_sim"
sim_top = "counter_tb"
sim_post_cmd = "xsim %s -gui" % sim_top
......
tests/counter/sim/vivado/vhdl/Manifest.py
View file @ f5fd4714
action = "simulation"
sim_tool = "vivado"
sim_tool = "vivado_sim"
sim_top = "counter_tb"
sim_post_cmd = "xsim %s -gui" % sim_top
......
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