Update Verilog counter test: counter + shifter

parent 1879e826
......@@ -10,6 +10,9 @@ module counter (
Q
);
//--------- Cycles per second -------------------------
parameter cycles_per_second = 12000000;
//--------- Output Ports ------------------------------
output [7:0] Q;
......@@ -17,14 +20,30 @@ module counter (
input clock, clear, count;
//--------- Internal Variables ------------------------
reg ready = 0;
reg [23:0] divider;
reg [7:0] Q;
//--------- Code Starts Here --------------------------
always @(posedge clock)
if (clear) begin
Q <= 8'b0 ;
end else if (count) begin
Q <= Q + 1;
end
always @(posedge clock) begin
if (ready)
begin
if (divider == cycles_per_second)
begin
divider <= 0;
Q <= {Q[6:0], Q[7]};
end
else
divider <= divider + 1;
end
else
begin
ready <= 1;
Q <= 8'b00010001;
divider <= 0;
end
end
endmodule
......@@ -8,6 +8,8 @@ module counter_tb();
reg clock, clear, count;
wire [7:0] Q;
defparam U_counter.cycles_per_second = 500;
// Initialize all variables
initial begin
$dumpfile("counter_tb.vcd");
......@@ -21,13 +23,13 @@ initial begin
#5 clear = 1; // Assert the clear signal
#10 clear = 0; // De-assert clear signal
#10 count = 1; // Start count
#2000 count = 0; // De-assert count enable
#10000 count = 0; // De-assert count enable
#5 $finish; // Terminate simulation
end
// Clock generator
always begin
#5 clock = ~clock; // Toggle clock every 5 ticks
#1 clock = ~clock; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
......
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