Skip to content

H
Hdlmake
Commit ff66fecd authored by Paweł Szostek's avatar Paweł Szostek
Browse files
Options

remove this bloody hdlmake_kernel.py

parent 59e57fec
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 518 additions and 424 deletions
src/action/__init__.py 0 → 100644
View file @ ff66fecd
#!/usr/bin/env python
from clean import CleanModules
from default import Default
from fetch import FetchModules
from fetch_makefile import GenerateFetchMakefile
from ise_makefile import GenerateISEMakefile
from ise_project import GenerateISEProject
from list_files import ListFiles
from list_modules import ListModules
from merge_cores import MergeCores
from quartus_project import GenerateQuartusProject
from remote_synthesis import GenerateRemoteSynthesisMakefile
from simulation import GenerateSimulationMakefile
src/action/action.py 0 → 100644
View file @ ff66fecd
#!/usr/bin/env python
import sys
import logging
from makefile_writer import MakefileWriter
class Action(object):
def __init__(self, modules_pool, options, env):
self.modules_pool = modules_pool
self.options = options
self.env = env
self.make_writer = MakefileWriter()
self._check_manifest()
self._check_env()
self._check_options()
@property
def top_module(self):
return self.modules_pool.get_top_module()
def _check_manifest(self):
pass
def _check_env(self):
pass
def _check_options(self):
pass
def run(self):
raise NotImplementedError()
def _check_all_fetched_or_quit(self):
pool = self.modules_pool
if not pool.is_everything_fetched():
logging.error("A module remains unfetched. "
"Fetching must be done prior to makefile generation")
print(str([str(m) for m in self.modules_pool if not m.isfetched]))
sys.exit("Exiting.")
src/action/clean.py 0 → 100644
View file @ ff66fecd
from action import Action
import logging
class CleanModules(Action):
def run(self):
logging.info("Removing fetched modules..")
remove_list = [m for m in self.modules_pool if m.source in ["svn", "git"] and m.isfetched]
remove_list.reverse() # we will remove modules in backward order
if len(remove_list):
for m in remove_list:
print("\t" + m.url + " [from: " + m.path + "]")
m.remove_dir_from_disk()
else:
logging.info("There are no modules to be removed")
\ No newline at end of file
src/action/default.py 0 → 100644
View file @ ff66fecd
import logging
import sys
from action import Action
from simulation import GenerateSimulationMakefile
from ise_project import GenerateISEProject
from quartus_project import GenerateQuartusProject
from ise_makefile import GenerateISEMakefile
from remote_synthesis import GenerateRemoteSynthesisMakefile
class Default(Action):
def run(self):
self._check_manifest()
tm = self.top_module
if not self.modules_pool.is_everything_fetched():
self.fetch(unfetched_only=True)
if tm.action == "simulation":
simulation_makefile = SimulationMakefile(modules_pool=self.modules_pool, options=self.options, env=self.env)
simulation_makefile.run()
elif tm.action == "synthesis":
if tm.target == "xilinx":
ise_project = ISEProject(modules_pool=self.modules_pool, options=self.options, env=self.env)
ise_project.run()
ise_makefile = ISEProject(modules_pool=self.modules_pool, options=self.options, env=self.env)
ise_makefile.run()
remote_synthesis = ISEProject(modules_pool=self.modules_pool, options=self.options, env=self.env)
remote_synthesis.run()
elif tm.target == "altera":
quartus_project = QuartusProject(modules_pool=self.modules_pool, options=self.options, env=self.env)
quartus_project.run()
else:
logging.error("Unrecognized target: %s" % tm.target)
sys.exit("Exiting")
def _check_manifest(self):
if self.top_module.action != "simulation" and self.top_module.action != "synthesis":
logging.error("'action' variable must be defined in the top manifest\n"
"Allowed values are: \"simulation\" or \"synthesis\"\n"
"This variable in a manifest file is necessary for Hdlmake\n"
"to be able to know what to do with the given modules' structure.\n"
"For more help type `hdlmake --help'\n"
"or visit http://www.ohwr.org/projects/hdl-make")
sys.exit("Exiting")
if self.top_module.syn_project is None:
logging.error("syn_project variable must be defined in the manifest")
sys.exit("Exiting")
src/action/fetch.py 0 → 100644
View file @ ff66fecd
import logging
from action import Action
class FetchModules(Action):
def run(self, unfetched_only=False):
logging.info("Fetching needed modules.")
self.modules_pool.fetch_all(unfetched_only)
logging.debug(str(self.modules_pool))
src/action/fetch_makefile.py 0 → 100644
View file @ ff66fecd
from action import Action
import logging
class GenerateFetchMakefile(Action):
def run(self):
pool = self.modules_pool
if pool.get_fetchable_modules() == []:
logging.error("There are no fetchable modules. "
"No fetch makefile is produced")
quit()
if not pool.is_everything_fetched():
logging.error("A module remains unfetched. "
"Fetching must be done prior to makefile generation")
quit()
self.make_writer.generate_fetch_makefile(pool)
src/action/ise_makefile.py 0 → 100644
View file @ ff66fecd
from __future__ import print_function
from action import Action
import logging
class GenerateISEMakefile(Action):
def run(self):
import global_mod
global_mod.mod_pool = self.modules_pool
logging.info("Generating makefile for local synthesis.")
ise_path = global_mod.env["ise_path"]
self.make_writer.generate_ise_makefile(top_mod=self.modules_pool.get_top_module(),
ise_path=ise_path)
src/action/ise_project.py 0 → 100644
View file @ ff66fecd
from __future__ import print_function
import logging
from action import Action
import sys
import os
from dependable_file import DependableFile
import dep_solver
from srcfile import SourceFileSet
from flow import ISEProject
from srcfile import SourceFileFactory
class GenerateISEProject(Action):
def run(self):
env = self.env
if self.env["ise_path"] is None:
logging.error("Can't generate an ISE project. ISE not found.")
quit()
else:
if not env["ise_version"]:
logging.error("Xilinx version cannot be deduced. Cannot generate ISE "
"project file properly. Please use syn_ise_version in the manifest "
"or set")
sys.exit("Exiting")
else:
logging.info("Generating project for ISE v. %d.%d" % (env["ise_version"][0], env["ise_version"][1]))
self._check_all_fetched_or_quit()
if os.path.exists(self.top_module.syn_project) or os.path.exists(self.top_module.syn_project + ".xise"):
self._handle_ise_project(update=True)
else:
self._handle_ise_project(update=False)
def _handle_ise_project(self, update=False):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
non_dependable = fileset.inversed_filter(DependableFile)
dependable = dep_solver.solve(fileset)
all_files = SourceFileSet()
all_files.add(non_dependable)
all_files.add(dependable)
prj = ISEProject(ise=self.env["ise_version"],
top_mod=self.modules_pool.get_top_module())
prj.add_files(all_files)
sff = SourceFileFactory()
logging.debug(top_mod.vlog_opt)
prj.add_files([sff.new(top_mod.vlog_opt)])
prj.add_libs(all_files.get_libs())
if update is True:
prj.load_xml(top_mod.syn_project)
else:
prj.add_initial_properties(syn_device=top_mod.syn_device,
syn_grade=top_mod.syn_grade,
syn_package=top_mod.syn_package,
syn_top=top_mod.syn_top)
prj.emit_xml(top_mod.syn_project)
src/action/list_files.py 0 → 100644
View file @ ff66fecd
#!/usr/bin/env python
from action import Action
class ListFiles(Action):
def run(self):
files_str = []
for m in self.modules_pool:
if not m.isfetched:
continue
files_str.append(self.options.delimiter.join([f.path for f in m.files]))
print(" ".join(files_str))
src/action/list_modules.py 0 → 100644
View file @ ff66fecd
from action import Action
import path
class ListModules(Action):
def run(self):
for m in self.modules_pool:
if not m.isfetched:
print("#!UNFETCHED")
print(m.url+'\n')
else:
print(path.relpath(m.path))
if m.source in ["svn", "git"]:
print("# "+m.url)
if m.parent:
print("# defined in %s" % m.parent.url)
else:
print("# root module")
if not len(m.files):
print(" # no files")
else:
for f in m.files:
print(" " + path.relpath(f.path, m.path))
print("")
src/action/merge_cores.py 0 → 100644
View file @ ff66fecd
from __future__ import print_function
import logging
from action import Action
from srcfile import VerilogFile, VHDLFile, NGCFile
from vlog_parser import VerilogPreprocessor
import dep_solver
import os.path
import time
class MergeCores(Action):
def run(self):
pool = self.modules_pool
if not pool.is_everything_fetched():
logging.error("A module remains unfetched. Fetching must be done prior to makefile generation")
print(str([str(m) for m in self.modules_pool.modules if not m.isfetched]))
quit()
flist = pool.build_very_global_file_list()
# if not os.path.exists(self.options.merge_cores):
# os.makedirs(self.options.merge_cores)
base = self.options.dest
f_out = open(base+".vhd", "w")
f_out.write("\n\n\n\n")
f_out.write("------------------------------ WARNING -------------------------------\n")
f_out.write("-- This code has been generated by hdlmake --merge-cores option --\n")
f_out.write("-- It is provided for your convenience, to spare you from adding --\n")
f_out.write("-- lots of individual source files to ISE/Modelsim/Quartus projects --\n")
f_out.write("-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n")
f_out.write("-- need to change something inside, edit the original source file --\n")
f_out.write("-- and re-genrate the merged version! --\n")
f_out.write("----------------------------------------------------------------------\n")
f_out.write("\n\n\n\n")
for vhdl in flist.filter(VHDLFile):
f_out.write("\n\n--- File: %s ----\n" % vhdl.rel_path())
f_out.write("--- source: %s\n" % vhdl.module.url)
f_out.write("--- last modified: %s\n" % time.ctime(os.path.getmtime(vhdl.path)))
f_out.write(open(vhdl.rel_path(), "r").read()+"\n\n")
#print("VHDL: %s" % vhdl.rel_path())
f_out.close()
f_out = open(base+".v", "w")
f_out.write("\n\n\n\n")
f_out.write("////////////////////////////// WARNING ///////////////////////////////\n")
f_out.write("// This code has been generated by hdlmake --merge-cores option //\n")
f_out.write("// It is provided for your convenience, to spare you from adding //\n")
f_out.write("// lots of individual source files to ISE/Modelsim/Quartus projects //\n")
f_out.write("// mainly for Windows users. Please DO NOT MODIFY this file. If you //\n")
f_out.write("// need to change something inside, edit the original source file //\n")
f_out.write("// and re-genrate the merged version! //\n")
f_out.write("//////////////////////////////////////////////////////////////////////\n")
f_out.write("\n\n\n\n")
for vlog in flist.filter(VerilogFile):
f_out.write("\n\n// File: %s\n" % vlog.rel_path())
f_out.write("// source: %s\n" % vlog.module.url)
f_out.write("// last modified: %s\n" % time.ctime(os.path.getmtime(vlog.path)))
vpp = VerilogPreprocessor()
for include_path in vlog.include_dirs:
vpp.add_path(include_path)
vpp.add_path(vlog.dirname)
f_out.write(vpp.preprocess(vlog.rel_path()))
f_out.close()
for ngc in flist.filter(NGCFile):
import shutil
print("NGC:%s " % ngc.rel_path())
shutil.copy(ngc.rel_path(), self.options.merge_cores+"/")
src/action/quartus_project.py 0 → 100644
View file @ ff66fecd
from __future__ import print_function
import logging
import os
from dependable_file import DependableFile
from action import Action
import dep_solver
from flow_altera import QuartusProject
class GenerateQuartusProject(Action):
def run(self):
if self.env["quartus_path"] is None:
logging.error("Can't generate a Quartus project. Quartus not found.")
quit()
else:
logging.info("Generating/updating Quartus project.")
self._check_all_fetched_or_quit()
if os.path.exists(self.top_module.syn_project) or os.path.exists(self.top_module.syn_project + ".qsf"):
self._update_existing_quartus_project()
else:
self._create_new_quartus_project()
def _create_new_quartus_project(self):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
non_dependable = fileset.inversed_filter(DependableFile)
fileset = dep_solver.solve(fileset)
fileset.add(non_dependable)
prj = QuartusProject(top_mod.syn_project)
prj.add_files(fileset)
prj.add_initial_properties(top_mod.syn_device,
top_mod.syn_grade,
top_mod.syn_package,
top_mod.syn_top)
prj.preflow = None
prj.postflow = None
prj.emit()
def _update_existing_quartus_project(self):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
non_dependable = fileset.inversed_filter(DependableFile)
fileset = dep_solver.solve(fileset)
fileset.add(non_dependable)
prj = QuartusProject(top_mod.syn_project)
prj.read()
prj.preflow = None
prj.postflow = None
prj.add_files(fileset)
prj.emit()
src/action/remote_synthesis.py 0 → 100644
View file @ ff66fecd
from action import Action
import logging
import os
import sys
from srcfile import SourceFileFactory
class GenerateRemoteSynthesisMakefile(Action):
def run(self):
self._check_all_fetched_or_quit()
logging.info("Generating makefile for remote synthesis.")
top_mod = self.modules_pool.get_top_module()
tcl = self._search_tcl_file()
if tcl is None:
self._generate_tcl()
tcl = "run.tcl"
files = self.modules_pool.build_very_global_file_list()
sff = SourceFileFactory()
files.add(sff.new(tcl, module=None))
files.add(sff.new(top_mod.syn_project, module=None))
self.make_writer.generate_remote_synthesis_makefile(files=files, name=top_mod.syn_name,
cwd=os.getcwd(), user=self.env["rsynth_user"],
server=self.env["rsynth_server"])
def _check_manifest(self):
if not self.top_module.action == "synthesis":
logging.error("action must be equal to \"synthesis\"")
sys.exit("Exiting")
if not self.top_module.syn_project:
logging.error("syn_project must be set in the manifest.")
sys.exit("Exiting")
def _search_tcl_file(self, directory=None):
if directory is None:
directory = "."
filenames = os.listdir(directory)
tcls = []
for filename in filenames:
file_parts = filename.split('.')
if file_parts[len(file_parts)-1] == "tcl":
tcls.append(filename)
if len(tcls) == 0:
return None
if len(tcls) > 1:
logging.warning("Multiple tcls in the current directory: " + str(tcls) + "\n" +
"Picking the first one: " + tcls[0])
return tcls[0]
def _generate_tcl(self):
f = open("run.tcl", "w")
f.write("project open " + self.top_module.syn_project + '\n')
f.write("process run {Generate Programming File} -force rerun_all\n")
f.close()
src/action/simulation.py 0 → 100644
View file @ ff66fecd
#!/usr/bin/env python
from __future__ import print_function
from action import Action
import logging
import dep_solver
import sys
class GenerateSimulationMakefile(Action):
def _check_manifest(self):
if not self.modules_pool.get_top_module().top_module:
logging.error("top_module variable must be set in the top manifest.")
sys.exit("Exiting")
def run(self):
self._check_all_fetched_or_quit()
self._check_manifest()
tm = self.modules_pool.top_module
if tm.sim_tool == "iverilog":
self._generate_iverilog_makefile()
elif tm.sim_tool == "isim":
self._generate_isim_makefile()
elif tm.sim_tool == "vsim" or tm.sim_tool == "modelsim":
self._generate_vsim_makefile()
else:
logging.error("Unrecognized or not specified simulation tool: %s" % str(tm.sim_tool))
sys.exit("Exiting")
def _generate_vsim_makefile(self):
# p.info("Generating makefile for simulation.")
if self.env["modelsim_path"] is None:
logging.error("Can't generate a Modelsim makefile. Modelsim not found.")
sys.exit("Exiting")
else:
logging.info("Generating ModelSim makefile for simulation.")
pool = self.modules_pool
top_module = pool.get_top_module()
flist = pool.build_global_file_list()
flist_sorted = dep_solver.solve(flist)
self.make_writer.generate_vsim_makefile(flist_sorted, top_module)
def _generate_isim_makefile(self):
# p.info("Generating makefile for simulation.")
if self.env["isim_path"] is None and self.env["xilinx"] is None:
logging.error("Can't generate an ISim makefile. ISim not found.")
sys.exit("Exiting")
else:
logging.info("Generating ISE Simulation (ISim) makefile for simulation.")
pool = self.modules_pool
top_module = pool.get_top_module()
flist = pool.build_global_file_list()
flist_sorted = dep_solver.solve(flist)
self.make_writer.generate_isim_makefile(flist_sorted, top_module)
def _generate_iverilog_makefile(self):
if self.env["iverilog_path"] is None:
logging.error("Can't generate an IVerilog makefile. IVerilog not found.")
sys.exit("Exiting")
else:
logging.info("Generating IVerilog makefile for simulation.")
pool = self.modules_pool
tm = pool.get_top_module()
flist = pool.build_global_file_list()
flist_sorted = dep_solver.solve(flist)
self.make_writer.generate_iverilog_makefile(flist_sorted, tm, pool)
src/hdlmake_kernel.py deleted 100644 → 0
View file @ 59e57fec
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment