Commits · 23be310b571bd3756b12081ef69981f1980898bc · Projects / Hdlmake · Open Hardware Repository

03 Jun, 2019 2 commits
- Merge branch '90-sufix-command-is-a-typo-rename-to-suffix-for-proper-english' into 'master' · 23be310b
  Tristan Gingold authored Jun 03, 2019
```
Resolve "--sufix command is a typo => rename to --suffix for proper english"

Closes #90

See merge request !2
```
  23be310b
- Merge branch '89-add-an-option-to-display-full-error-log-in-case-of-an-error' into 'master' · f9366683
  Tristan Gingold authored Jun 03, 2019
```
Resolve "Add an option to display full error log in case of an error"

Closes #89

See merge request !1
```
  f9366683
01 May, 2019 1 commit
- Replaced sufix with suffix · ba0b8136
  Nicolas Chevillot authored May 01, 2019
  
  ba0b8136
30 Apr, 2019 3 commits
- Renamed sufix into suffix · 3a026a10
  Nicolas Chevillot authored Apr 30, 2019
  
  3a026a10
- Moved try/exception in the main function · d542495d
  Nicolas Chevillot authored Apr 30, 2019
  
  d542495d
- Added traceback · daacc1b9
  Nicolas Chevillot authored Apr 30, 2019
  
  daacc1b9
11 Apr, 2019 2 commits
- Bump version to 3.2 · c4b5fced
  Javier D. Garcia-Lasheras authored Apr 11, 2019
  
  c4b5fced
- Update docs with the new Quartus property dictionary format · 54db6764
  Javier D. Garcia-Lasheras authored Apr 11, 2019
  
  54db6764
09 Apr, 2019 1 commit
- Fix for issue #35 , improve ifdef matching in Verilog parser · e56bcca8
  Javier D. Garcia-Lasheras authored Apr 09, 2019
  
  e56bcca8
04 Apr, 2019 2 commits
- Provide the Quartus properties as a dictionary · edb220cb
  Javier D. Garcia-Lasheras authored Apr 04, 2019
  
  edb220cb
- Escape quotations in the Quartus Makefile user properties · 63139ec6
  Javier D. Garcia-Lasheras authored Apr 04, 2019
  
  63139ec6
03 Apr, 2019 2 commits
- Do not try to synthesize Verilog and SystemVerilog includes · 71b60dde
  Javier D. Garcia-Lasheras authored Apr 03, 2019
  
  71b60dde
- Do not enable SystemVerilog 2005 in Quartus, but support syn_properties in the Manifest · a348e326
  Javier D. Garcia-Lasheras authored Apr 03, 2019
  
  a348e326
02 Apr, 2019 3 commits
- Enable SystemVerilog 2005 as default Verilog input version in Quartus · 2f5ab537
  Javier D. Garcia-Lasheras authored Apr 02, 2019
  
  2f5ab537
- Add include_dirs as SEARCH_PATH in Quartus · 49cc92e6
  Javier D. Garcia-Lasheras authored Apr 02, 2019
  
  49cc92e6
- Fix System Verilog files included on Verilog synthesis list · 6bda472d
  Javier D. Garcia-Lasheras authored Apr 02, 2019
  
  6bda472d
01 Apr, 2019 1 commit
- Hot Fix include_dirs mechanism · ba831ab5
  Javier D. Garcia-Lasheras authored Apr 01, 2019
  
  ba831ab5
30 Mar, 2019 11 commits
- Bump version to 3.1 · ffa3ba6c
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  ffa3ba6c
- Fix typo in Xilinx ISim at the supported tools table in docs · ecef800f
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  ecef800f
- Fix missing makefile command in the prefix and sufix examples · e826f6e1
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  e826f6e1
- Fix and upgrade the counter test demo HDL files · c97cff89
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  c97cff89
- Improve how new_dep_solver handles a missing top_module definition · 1627ac83
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  1627ac83
- Adjust links in the documents to the new GitLab management · b3a15d2d
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  b3a15d2d
- Quit upon error should generate an error code different than 0 · d8233b71
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  d8233b71
- Include a note in the docs about Modelsim +incdir+ management · 4c8d351c
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  4c8d351c
- Test of Active-HDL failes under CMD · 302aab7d
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  302aab7d
- Fix Active-HDL support in Windows Cmd and PowerShell · 2431e387
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  2431e387
- Fix file source handling in Diamond and Libero · 13f5d20e
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  13f5d20e
29 Mar, 2019 5 commits
- More helpful error message when no action set causing tool not to be set. · 7959a8de
  William Kamp authored Jul 25, 2018
  
  7959a8de
- Better support multiple VHDL libraries. · 033590e1
  William Kamp authored Jul 25, 2018
```
VHDL_parser.py extracts the library from instantiations.
new_dep_solver.py does not assume the work library.
core.py inherits the library from the parent Manifest.
```
  033590e1
- Fix incl_makefiles being ignored at synthesis and simulation · 26f08930
  Javier D. Garcia-Lasheras authored Mar 29, 2019
  
  26f08930
- Fix ISIM support for mixed HDL languages · 4043e15b
  Javier D. Garcia-Lasheras authored Mar 29, 2019
  
  4043e15b
- XCO files should be handled by ISE, not only by Vivado and PlanAhead. · d3824c98
  Javier D. Garcia-Lasheras authored Mar 29, 2019
  
  d3824c98
21 Dec, 2018 4 commits
- Fix project links in the docs to match the new OHWR.org site features · bc1e6796
  Javier D. Garcia-Lasheras authored Dec 21, 2018
  
  bc1e6796
- Report an error and quit when the manifest file is not found · cd664d09
  Javier D. Garcia-Lasheras authored Dec 21, 2018
  
  cd664d09
- Fix and document Xilinx Vivado and PlanAhead project language selection · b112db0d
  Javier D. Garcia-Lasheras authored Dec 21, 2018
  
  b112db0d
- Include the Xilinx BMM files in Vivado, ISE and PlanAhead · 530d2f14
  Javier D. Garcia-Lasheras authored Dec 21, 2018
  
  530d2f14
30 Nov, 2018 1 commit
- Document and effectively support ghdl_opt setting. · 968fa87d
  Tristan Gingold authored Nov 30, 2018
  
  968fa87d
21 Mar, 2018 2 commits
- Fix bug 1761: VHDL instantiations with archietecture selection · f38d03cd
  Adrian Fiergolski authored Mar 21, 2018
  
  f38d03cd
- Fix bug 1760: entity and architecture declaration in mutiple files. · 1a5fc8ee
  Adrian Fiergolski authored Mar 21, 2018
  
  1a5fc8ee