Hdlmake:4c8d351cd0a2033b6099d9672777cb8312329cc1 commitshttps://ohwr.org/project/hdl-make/commits/4c8d351cd0a2033b6099d9672777cb8312329cc12019-03-30T01:33:43Zhttps://ohwr.org/project/hdl-make/commit/4c8d351cd0a2033b6099d9672777cb8312329cc1Include a note in the docs about Modelsim +incdir+ management2019-03-30T01:33:43ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/302aab7dc159dc182a7e31efbebc9e9ab9dc801cTest of Active-HDL failes under CMD2019-03-30T00:54:39ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/2431e3874150ddf38a6fba8feff4d7493ca29267Fix Active-HDL support in Windows Cmd and PowerShell2019-03-30T00:50:24ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/13f5d20ee8d3cd8077a350b71f5a04d7cfd77edeFix file source handling in Diamond and Libero2019-03-30T00:43:09ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/7959a8deabd98258bba3a4d6b8f934f1448f9102More helpful error message when no action set causing tool not to be set.2019-03-29T23:12:00ZWill Kampwillkamp@gmail.comhttps://ohwr.org/project/hdl-make/commit/033590e18cf27a8513928846321fb25e6ababc40Better support multiple VHDL libraries.2019-03-29T23:11:00ZWill Kampwillkamp@gmail.com
VHDL_parser.py extracts the library from instantiations.
new_dep_solver.py does not assume the work library.
core.py inherits the library from the parent Manifest.
https://ohwr.org/project/hdl-make/commit/26f08930699c2bcf4ba95bacbdc74b979b1cabc5Fix incl_makefiles being ignored at synthesis and simulation2019-03-29T22:02:02ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/4043e15bc82674be2c7721a64a0f21cec6015d68Fix ISIM support for mixed HDL languages2019-03-29T18:47:54ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/d3824c98f324d7e5a1c7ede226113148ed683ce5XCO files should be handled by ISE, not only by Vivado and PlanAhead.2019-03-29T17:18:42ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/bc1e679605f718bbfa3c8599715bb4890f1f7501Fix project links in the docs to match the new OHWR.org site features2018-12-21T20:05:33ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/cd664d09a2943b63c2d4426e4b54ca8dec725636Report an error and quit when the manifest file is not found2018-12-21T19:51:58ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/b112db0d26f19d2a306906ca44b76e50e9751391Fix and document Xilinx Vivado and PlanAhead project language selection2018-12-21T19:34:54ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/530d2f14910cef3dc9f0747aacab8481b9fc7584Include the Xilinx BMM files in Vivado, ISE and PlanAhead2018-12-21T18:40:54ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/968fa87d38fb65ad56dbc7e3e2131a89c0635e88Document and effectively support ghdl_opt setting.2018-11-30T09:27:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/hdl-make/commit/f38d03cdbc05cf03b42ed12512fce6e5fa6e07bbFix bug 1761: VHDL instantiations with archietecture selection2018-03-21T12:17:32ZAdrian Fiergolskiadrian.fiergolski@cern.chhttps://ohwr.org/project/hdl-make/commit/1a5fc8eeed54f4beb2af4365eb16522cf1a42a8aFix bug 1760: entity and architecture declaration in mutiple files.2018-03-21T10:22:16ZAdrian Fiergolskiadrian.fiergolski@cern.chhttps://ohwr.org/project/hdl-make/commit/db4e1ab6456ce6b949b166da3afb953b25d4eb4aPrevent tool from compiling (system)verilog included files.2018-03-07T14:37:57ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/hdl-make/commit/943c08c5c3c9847680144574a345c1f33000e77cMake "none" the default top_module if not specified in Manifest.2018-02-19T23:20:52ZWill Kampwkamp@aut.ac.nzhttps://ohwr.org/project/hdl-make/commit/01411df9874084d8197c1cbc31cd5fd80aacb0ecWhen listing files use top_module from the Manifest, overwite with --top argu...2018-02-12T05:14:13ZWill Kampwkamp@aut.ac.nzhttps://ohwr.org/project/hdl-make/commit/e8c1f12ca59ee01e617a1de248cd9f5e3390760dRecognise entire VHDL functions and entity instanciations as instances. 2018-02-12T04:22:15ZWill Kampwkamp@aut.ac.nz
Gobble entire VHDL function to avoid input parameters being recognised as instances.
Entity instanciations recognised as instances as well - borrowed from rjen's commit <a href="/project/hdl-make/commit/d0ba0268fc1d9303380daa2b386c046d0634b933" data-original="d0ba0268fc1d9303380daa2b386c046d0634b933" data-link="false" data-link-reference="false" data-project="10721" data-commit="d0ba0268fc1d9303380daa2b386c046d0634b933" data-reference-type="commit" data-container="body" data-placement="bottom" title="Modified: - instance regex supports entity instantiation" class="gfm gfm-commit has-tooltip">d0ba0268</a> on feat_svn_ise branch.https://ohwr.org/project/hdl-make/commit/40d233693aa6063b9a88bc8428c95431a281d777Fix sufix code, append to sufix code rather than prefix code.2018-02-12T04:14:36ZWill Kampwkamp@aut.ac.nzhttps://ohwr.org/project/hdl-make/commit/d0d037d3c0db263f76b433180f460a069db962a5SystemVerilog and Verilog file descriptions looked to be flipped in quartus.py2017-09-29T15:40:52ZJoshua A. Einstein-Curtisjeinstei@fnal.govhttps://ohwr.org/project/hdl-make/commit/2712f107097cdac62793fc8f1b4f0420ec47cd26Introduce the language Manifest variable and use it for Xilinx tools2017-06-19T01:18:06ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/48714bcc0eb7c614e29106cdb2a2b0e9bd285514Fix some typos and indentation issues in the Modelsim example documentation2017-06-15T11:11:33ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/00ff29023de589c56932a0d8e4ec95a942cd2702Fix typo in the documentation for Modelsim advanced example2017-06-15T04:02:22ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/c317958529b76eb8215b235a8357954a546bcabeDocument the fetcher providing Git submodule functionality2017-06-15T03:57:27ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/9a38342501143a0b34558996199b449e42aa8799Document modelsim_ini_path and extra_modules Manifest variables2017-06-15T03:41:45ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/d7236dac020f59acb27425ad4efb8db8a5d9314bDocument the use all file optional argument2017-06-15T03:28:55ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/809f1da5b79c085a76516e4e6dbc89e2b8639aafAdd documentation for the --logfile option2017-06-15T03:22:22ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/bc1607fd8360c113318920464694917a67fa62b6Added advanced simulation example for Modelsim2017-06-15T03:13:22ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/0a4658e0fa1938fd4cda1cffd36e99df8babfd9bSolve files even when the option for using all of them is enabled2017-06-14T17:35:58ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/30c59ca5b51ae17fdf0d62a2d0805cd93bab9bdbAdd support for custom modelsim_ini_path in Modelsim Manifest.py and Makefile2017-06-14T17:12:42ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/45c6b6495348dc0b66875d0baa845cd56c018f4bFix include_dirs variable support for Vsim-like tools2017-06-14T15:40:00ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/cae14d1503fb57bc7d41c23a6da0b53a5ffda053Fix URL and version parsing in the SVN fetcher2017-06-14T14:10:14ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/68c1b82fa9014e3dcfd4d1a97824c09e1d1ffa8cFix broken SVN fetcher2017-06-14T13:02:58ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/5baf592b858efe8ca3580662b6d259ff979581a6Fixed issue allowing to scan dependencies by instance on the VHDL parser2017-06-14T12:42:42ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/a2956203a4a96f59cfaf945b673aefd8b335e8c9Finish the program if not all of the modules are fetched2017-06-13T13:49:32ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/0dcb9508ae8ae5d689f59b4029f6a1ea5813d848Add support for Xilinx XST Constraint File in Vivado2017-06-13T13:45:50ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/c0fdb014f88d69b69eedd41c04d2fc66c6190f43Use a Git submodule fetcher to replace the unstable automatic submodule scan2017-06-13T10:52:30ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/b497b688d7f0aff627d13bed424f18de1a3b0b9aFix issue when listing files from outside the top directory2017-06-13T05:47:51ZJavier Garciajgarcia@gl-research.com