Commits · 7feedf4d11624810fe5918af9aed8b2d4d14eb71 · Projects / Hdlmake · Open Hardware Repository

10 Mar, 2017 2 commits
- Update the VHDL counter test · 7feedf4d
  Javier D. Garcia-Lasheras authored Mar 10, 2017
  
  7feedf4d
- Update Verilog counter test: counter + shifter · feff4994
  Javier D. Garcia-Lasheras authored Mar 10, 2017
  
  feff4994
09 Mar, 2017 3 commits
- Add the counter test for IceStorm synthesis · 1879e826
  Javier D. Garcia-Lasheras authored Mar 09, 2017
  
  1879e826
- Initial support for IceStorm synthesis · 852c1f43
  Javier D. Garcia-Lasheras authored Mar 09, 2017
  
  852c1f43
- Refactor the TCL section generation code · a257c698
  Javier D. Garcia-Lasheras authored Mar 09, 2017
  
  a257c698
08 Mar, 2017 3 commits
- More elegant TCL code on the Xilinx ISE Makefile section for files · 0735b9a0
  Javier D. Garcia-Lasheras authored Mar 08, 2017
  
  0735b9a0
- Support for syn_properties variable in Xilinx ISE · 7de23880
  Javier D. Garcia-Lasheras authored Mar 08, 2017
  
  7de23880
- Read the commit id from the Git submodule if available · 81f8c750
  Javier D. Garcia-Lasheras authored Mar 08, 2017
  
  81f8c750
06 Mar, 2017 4 commits
- Purge the unused synthesis stages for each of the supported tools · 3427cf5f
  Javier D. Garcia-Lasheras authored Mar 06, 2017
  
  3427cf5f
- Remove blank line from Xilinx TCL error checking · 754e247d
  Javier D. Garcia-Lasheras authored Mar 06, 2017
  
  754e247d
- Add error checking in synthesis for Xilinx PlanAhead and Vivado · 91c3b301
  Javier D. Garcia-Lasheras authored Mar 06, 2017
  
  91c3b301
- Only add the ip_repo_paths property if the dir list is not empty · f6a02063
  Javier D. Garcia-Lasheras authored Mar 06, 2017
  
  f6a02063
05 Mar, 2017 4 commits
- HDLMake creates a Makefile, not a project: fix message · c7cc50b5
  Javier D. Garcia-Lasheras authored Mar 05, 2017
  
  c7cc50b5
- Delete extension from project name if provided at the Manifest.py -- fix indentation · eaf8c8ce
  Javier D. Garcia-Lasheras authored Mar 05, 2017
  
  eaf8c8ce
- Delete extension from project name if provided at the Manifest.py · 071810dc
  Javier D. Garcia-Lasheras authored Mar 05, 2017
  
  071810dc
- Add error checking on the ISE synthesis TCL scripts · b1192242
  Javier D. Garcia-Lasheras authored Mar 05, 2017
  
  b1192242
04 Mar, 2017 1 commit
- Clean only the Quartus project .qsf file, not every .qsf · 66c41063
  Javier D. Garcia-Lasheras authored Mar 04, 2017
  
  66c41063
03 Mar, 2017 3 commits
- Fix some issues related with Intel Quartus .qpf and .qsf files · cba64d46
  Javier D. Garcia-Lasheras authored Mar 03, 2017
  
  cba64d46
- Use a separated TCL file for each synthesis stage · e758cc82
  Javier D. Garcia-Lasheras authored Mar 03, 2017
  
  e758cc82
- Improve project management for Xilinx ISE · dc736d95
  Javier D. Garcia-Lasheras authored Mar 03, 2017
  
  dc736d95
19 Feb, 2017 1 commit
- Execute each Manifest from the folder in which it resides · f7598b52
  Javier D. Garcia-Lasheras authored Feb 19, 2017
  
  f7598b52
14 Feb, 2017 8 commits
- Fixing hierarchical support for Intel Quartus · 05e6060a
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  05e6060a
- Fixing hierarchical support for Modelsim · b5695a66
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  b5695a66
- Fixing hierarchical support for Xilinx ISim · ca39728f
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  ca39728f
- Fixing hierarchical support for Xilinx Vivado · 204210d6
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  204210d6
- Fixing hierarchical support for Xilinx ISE · 2a88a919
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  2a88a919
- Fixing hierarchical support for Icarus Verilog · b0b3990a
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  b0b3990a
- Fixing hierarchical support for GHDL · ceac87ea
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  ceac87ea
- First tests towards hierarchical behavior · 28035599
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  28035599
21 Nov, 2016 2 commits
- Add syn & sim properties to Manifest.py and use it to provide custom settings to… · 03455340
  Javier D. Garcia-Lasheras authored Nov 21, 2016
```
Add syn & sim properties to Manifest.py and use it to provide custom settings to the newer Xilinx tools
```
  03455340
- Disable manual implementation compile order in ISE · 7eafb912
  Javier D. Garcia-Lasheras authored Nov 21, 2016
  
  7eafb912
17 Nov, 2016 5 commits
- Add System Exit exception handler to the Manifest parser · 12c7799b
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  12c7799b
- Add VHDL and Verilog template files support to Vivado · ec10c20b
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  ec10c20b
- Add RAM file support to Vivado · 92c32a9f
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  92c32a9f
- Add Xilinx Coefficient and Memory Initialization files · 3285708c
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  3285708c
- Hack a known Vivado issue by using IS_GLOBAL_INCLUDE · 879eca7f
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  879eca7f
24 Sep, 2016 2 commits
- Launch Vivado in TCL mode · 6255c9ba
  Javier D. Garcia-Lasheras authored Sep 24, 2016
  
  6255c9ba
- Add support for Xilinx XDC and XCI files on Vivado · 42ddedf5
  Javier D. Garcia-Lasheras authored Sep 24, 2016
  
  42ddedf5
19 Sep, 2016 1 commit
- Bump version to 3.0 · 0d6f5be2
  Javier D. Garcia-Lasheras authored Sep 19, 2016
  
  0d6f5be2
07 Sep, 2016 1 commit
- Fix ISim not getting the right 'ini' file · 66d9f8e8
  Javier D. Garcia-Lasheras authored Sep 07, 2016
  
  66d9f8e8