Commits · f38d03cdbc05cf03b42ed12512fce6e5fa6e07bb · Projects / Hdlmake · Open Hardware Repository

21 Mar, 2018 2 commits
- Fix bug 1761: VHDL instantiations with archietecture selection · f38d03cd
  Adrian Fiergolski authored Mar 21, 2018
  
  f38d03cd
- Fix bug 1760: entity and architecture declaration in mutiple files. · 1a5fc8ee
  Adrian Fiergolski authored Mar 21, 2018
  
  1a5fc8ee
07 Mar, 2018 1 commit
- Prevent tool from compiling (system)verilog included files. · db4e1ab6
  Tomasz Wlostowski authored Feb 05, 2018
  
  db4e1ab6
19 Feb, 2018 1 commit
- Make "none" the default top_module if not specified in Manifest. · 943c08c5
  Will Kamp authored Feb 19, 2018
  
  943c08c5
12 Feb, 2018 3 commits
- When listing files use top_module from the Manifest, overwite with --top argument. · 01411df9
  Will Kamp authored Feb 12, 2018
  
  01411df9
- Recognise entire VHDL functions and entity instanciations as instances. · e8c1f12c
  Will Kamp authored Feb 12, 2018
```
Gobble entire VHDL function to avoid input parameters being recognised as instances.
Entity instanciations recognised as instances as well - borrowed from rjen's commit d0ba0268 on feat_svn_ise branch.
```
  e8c1f12c
- Fix sufix code, append to sufix code rather than prefix code. · 40d23369
  Will Kamp authored Feb 12, 2018
  
  40d23369
29 Sep, 2017 1 commit
- SystemVerilog and Verilog file descriptions looked to be flipped in quartus.py · d0d037d3
  Joshua A. Einstein-Curtis authored Sep 29, 2017
  
  d0d037d3
19 Jun, 2017 1 commit
- Introduce the language Manifest variable and use it for Xilinx tools · 2712f107
  Javier D. Garcia-Lasheras authored Jun 19, 2017
  
  2712f107
15 Jun, 2017 7 commits
- Fix some typos and indentation issues in the Modelsim example documentation · 48714bcc
  Javier D. Garcia-Lasheras authored Jun 15, 2017
  
  48714bcc
- Fix typo in the documentation for Modelsim advanced example · 00ff2902
  Javier D. Garcia-Lasheras authored Jun 15, 2017
  
  00ff2902
- Document the fetcher providing Git submodule functionality · c3179585
  Javier D. Garcia-Lasheras authored Jun 15, 2017
  
  c3179585
- Document modelsim_ini_path and extra_modules Manifest variables · 9a383425
  Javier D. Garcia-Lasheras authored Jun 15, 2017
  
  9a383425
- Document the use all file optional argument · d7236dac
  Javier D. Garcia-Lasheras authored Jun 15, 2017
  
  d7236dac
- Add documentation for the --logfile option · 809f1da5
  Javier D. Garcia-Lasheras authored Jun 15, 2017
  
  809f1da5
- Added advanced simulation example for Modelsim · bc1607fd
  Javier D. Garcia-Lasheras authored Jun 15, 2017
  
  bc1607fd
14 Jun, 2017 6 commits
- Solve files even when the option for using all of them is enabled · 0a4658e0
  Javier D. Garcia-Lasheras authored Jun 14, 2017
  
  0a4658e0
- Add support for custom modelsim_ini_path in Modelsim Manifest.py and Makefile · 30c59ca5
  Javier D. Garcia-Lasheras authored Jun 14, 2017
  
  30c59ca5
- Fix include_dirs variable support for Vsim-like tools · 45c6b649
  Javier D. Garcia-Lasheras authored Jun 14, 2017
  
  45c6b649
- Fix URL and version parsing in the SVN fetcher · cae14d15
  Javier D. Garcia-Lasheras authored Jun 14, 2017
  
  cae14d15
- Fix broken SVN fetcher · 68c1b82f
  Javier D. Garcia-Lasheras authored Jun 14, 2017
  
  68c1b82f
- Fixed issue allowing to scan dependencies by instance on the VHDL parser · 5baf592b
  Javier D. Garcia-Lasheras authored Jun 14, 2017
  
  5baf592b
13 Jun, 2017 4 commits
- Finish the program if not all of the modules are fetched · a2956203
  Javier D. Garcia-Lasheras authored Jun 13, 2017
  
  a2956203
- Add support for Xilinx XST Constraint File in Vivado · 0dcb9508
  Javier D. Garcia-Lasheras authored Jun 13, 2017
  
  0dcb9508
- Use a Git submodule fetcher to replace the unstable automatic submodule scan · c0fdb014
  Javier D. Garcia-Lasheras authored Jun 13, 2017
  
  c0fdb014
- Fix issue when listing files from outside the top directory · b497b688
  Javier D. Garcia-Lasheras authored Jun 13, 2017
  
  b497b688
12 Jun, 2017 4 commits
- Use a less agressive but more formal VHDL parsing approach · 2347f124
  Javier D. Garcia-Lasheras authored Jun 12, 2017
  
  2347f124
- Add the extra_modules option to force the inclusion of HDL modules in the solved file hierarchy · 0ded0fa7
  Javier D. Garcia-Lasheras authored Jun 12, 2017
  
  0ded0fa7
- Add an option to use a log file, this will made debugging easier · 477c281a
  Javier D. Garcia-Lasheras authored Jun 12, 2017
  
  477c281a
- Improved functionality for the web based GUI interface · 3c9acec4
  Javier D. Garcia-Lasheras authored Jun 12, 2017
  
  3c9acec4
11 Jun, 2017 1 commit
- Introduce some improvements in the VHDL parser · 267e6232
  Javier D. Garcia-Lasheras authored Jun 11, 2017
  
  267e6232
10 Jun, 2017 2 commits
- Abort execution if we find an unknown source file type · 3a97ba42
  Javier D. Garcia-Lasheras authored Jun 10, 2017
  
  3a97ba42
- Add more Cyclone family macros in Intel Quartus · a78ed644
  Javier D. Garcia-Lasheras authored Jun 10, 2017
  
  a78ed644
09 Jun, 2017 7 commits
- Use the relative path as the module folder route · b888a3ed
  Javier D. Garcia-Lasheras authored Jun 09, 2017
  
  b888a3ed
- Add an option to disable the dependency solver and to use the complete file set · a7f5f158
  Javier D. Garcia-Lasheras authored Jun 09, 2017
  
  a7f5f158
- Purge old source files from the Xilinx ISE project before sourcing files.tcl · bdd55365
  Javier D. Garcia-Lasheras authored Jun 09, 2017
  
  bdd55365
- Scanning for Git submodules is now an option, not enabled by default · 618a8956
  Javier D. Garcia-Lasheras authored Jun 09, 2017
  
  618a8956
- Fix a line too long style issue in a comment placed at the module.py file · 79b56ce2
  Javier D. Garcia-Lasheras authored Jun 09, 2017
  
  79b56ce2
- Temporarly enable the Git submodules feature as a default · 2d07933d
  Javier D. Garcia-Lasheras authored Jun 09, 2017
  
  2d07933d
- Don't crash if don't find the Manifest.py · 055a91aa
  Javier D. Garcia-Lasheras authored Jun 09, 2017
  
  055a91aa