Hdlmake issueshttps://ohwr.org/project/hdl-make/issues2019-02-12T09:35:28Zhttps://ohwr.org/project/hdl-make/issues/81Finish gdhl support in simulation makefiles2019-02-12T09:35:28ZPaweł SzostekFinish gdhl support in simulation makefilesThe correspondent work is put in ghdl branchJavier D. Garcia-LasherasJavier D. Garcia-Lasherashttps://ohwr.org/project/hdl-make/issues/80Finish quartus support2019-02-12T09:35:28ZPaweł SzostekFinish quartus supportThe correspondent work is present in quartus branchPaweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/79Add more logic into ise version detection2019-02-12T09:35:27ZPaweł SzostekAdd more logic into ise version detectionThe appropriate ISE path can be found using 'which' command. With
'which' one can find path to used binaries. When going up in the
directory structure, there is a chance that you will reach a directory,
whose name indicates the version.
The same must be done in remote synthesis (which involves developing
some in-line makefile script).Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/78python version2019-02-12T09:35:27ZAlessandro Rubinipython versionI've an older debian, with python 2.5
hdlmake is not working and spits an unphatomable error.
The problem is that zipfile autodecompression was introduced
in version 2.6, and when you run "make" to build hdlmake itself
(the zip file) the version is not checked.
Maybe it should be checked, although I'm aware most people doesn't
use old tools.https://ohwr.org/project/hdl-make/issues/77hdlmake --ise-proj2019-02-12T09:35:26ZCesar Pradoshdlmake --ise-projhdlmake --ise-proj fails because it is not able to determine the version
of xst. You're trying to get the version from the insatllation folder,
at least in the last installations of ise I don't have any more the
version in the path and I think that it is not the best solution. I
couldn't find a neat way of getting the version of xst, but at least I
can get by with this:
$xst --help
Release 13.2 .....
I have modified the source code where you're looking for the soft
version with $which xst and it is working, if you find a better way,
better, if not I would rely on the installation path.https://ohwr.org/project/hdl-make/issues/76typo in help message2019-02-12T09:35:26ZProjectstypo in help messageThe description for --list-files says "List all files in a from of a
space-separated string".
Should be form instead of from -\> "List all files in a form of a
space-separated string".Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/75fetch tag/commit2019-02-12T09:35:25ZProjectsfetch tag/commitAdd the ability to fetch a particular git tag or commit for a module.
\-\> With a special synthesis in the Manifest file.Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/74Add possibility to pass user defined variables2019-02-12T09:35:25ZProjectsAdd possibility to pass user defined variablesAdd possibility to pass user defined variables from the root Manifest to
the others Manifests.Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/73Fix a bug in dependency generation2019-02-12T09:35:24ZPaweł SzostekFix a bug in dependency generationVamsi Vytla:
In file 'dep\_solver.py': f.\_dep\_fixed is set when
get/set\_dep\_requires/provides are invoked. Suppose, the variable
'\_dep\_fixed' for 'file\_2.v' gets set in the invocation of
'\_*create\_deps()' during the call '*\_lookup\_post\_provider()' for
'file\_1.v', then the solver never gets a chance to set the post
provider for 'file\_2.v' before 'file\_2.v' in the fset.Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/72Add "Create Binary Configuration File" option by default when creating xise p...2019-02-12T09:35:24ZProjectsAdd "Create Binary Configuration File" option by default when creating xise project file.By default, when creating the xise project file, the option to generate
a .bin file should be
activated.
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/70Add vhd file generation during build2019-02-12T09:35:22ZProjectsAdd vhd file generation during buildEvery time a bitstream is build, a vhd file should be created.
This vhd file can be used to embed information to the bitstream.
The file should contain (to be discussed):
\> 1. Synthesis tool name+version
\> 2. Git top-module name+url
\> 3. Full git hash of the top-module
\> 4. Name of the person synthesizing (unix id)
\> 5. Date of the the synthesis
The idea is to be able to read this information from outside the FPGA to
uniquely identify a bitstream.Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/69Not fetching to the right dir2019-02-12T09:35:22ZProjectsNot fetching to the right dirOn isyp branch, hdlmake is not fetching/looking in the "fetch\_to"
directory.
For example, if I want to make a simulation Makefile, fetched modules
have to be in the simulation directory for hdlmake to work.
Otherwise it gives:
mcattin@pcbe15575:~/project/fmc\_adc\_100ms/hdl/spec/sim$ hdlmake
--make-sim
Generating makefile for simulation...
A module remains unfetched. Fetching must be done prior to makefile
generation
Oooops\! We've got an error. Here is the appropriate info:
Hdlmake build 2012Jul27:ed84c9
Traceback (most recent call last):
File "/usr/bin/hdlmake/*main*.py", line 139, in main
getattr(kernel, function)()
File "/usr/bin/hdlmake/hdlmake\_kernel.py", line 102, in
generate\_modelsim\_makefile
p.echo(str(\[str(m) for m in self.modules\_pool.modules if not
m.isfetched\]))
AttributeError: 'ModulePool' object has no attribute 'modules'Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/67Wrong help message2019-02-12T09:35:21ZProjectsWrong help messageThe help message says:
`usage: hdlmake [command] [options]`
But in fact the option must come before the command\!
Otherwise we got:
`$ hdlmake-master list-mods --log debug
usage: hdlmake [command] [options]
hdlmake: error: unrecognized arguments: --log debug`Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/66list-mods command throwing TypeError2019-02-12T09:35:20ZProjectslist-mods command throwing TypeErrorWhen trying to run: `$ hdlmake-master list-mods` on the following
project:
url: git:https://www.ohwr.org/hdl-core-lib/gn4124-core.git
sha: 3844fe59dab7b66f46698e348c16e252f93e4cc3
I get the following error:
`~/project/gn4124_core/hdl/spec/syn$ hdlmake-master list-mods
/opt/Xilinx/13.3/ISE_DS/bin/lin/vlogcomp
/bin/sh: /opt/Xilinx/13.3/ISE_DS/bin/lin/vlogcomp: No such file or
directory
#path source
. 3
../rtl 3
../../common/rtl 3
../../gn4124core/rtl 3
ERROR __main__.py:218: main() 'NoneType' object has no attribute
'__getitem__'
Trace:
Traceback (most recent call last):
File "/home/mcattin/project/hdl-make/hdlmake/__main__.py", line 215, in
main
action_instance.run()
File "/home/mcattin/project/hdl-make/hdlmake/action/list_modules.py",
line 53, in run
print("%s\t%s" % (path.relpath(m.path), m.source))
File "/home/mcattin/project/hdl-make/hdlmake/util/path.py", line 123, in
relpath
if p2[-1] == '/':
TypeError: 'NoneType' object has no attribute '__getitem__'`Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/63ISE: Files missing from make clean2019-02-12T09:35:19ZTom LevensISE: Files missing from make cleanThe following files are missing from the `ISE_CRAP` variable in the
makefile and don't get cleaned by `make clean`:
- `${syn_top}.bgn`
- `par_usage_statistics.html`https://ohwr.org/project/hdl-make/issues/62syn_post_cmd not run by make2019-02-12T09:35:18ZTom Levenssyn_post_cmd not run by makeThe `syn_post_cmd` is not run after sythesis when running make (with no
options). I would suggest altering the structure of the Makefile to work
around this:
#target for performing local synthesis
local: syn_pre_cmd check_tool syn_local_cmd syn_post_cmd
syn_local_cmd:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
check_tool:
echo Running check_tool
syn_post_cmd:
echo Running syn_post_cmd
syn_pre_cmd:
echo Running syn_pre_cmd
Now all commands are run as expected. I would suggest also removing the
dependancy of `syn_post_cmd: local` so the command can be run without
re-synthesising.https://ohwr.org/project/hdl-make/issues/61syn_*_cmd multiline2019-02-12T09:35:18ZTom Levenssyn_*_cmd multilineIt would be nice if `syn_pre_cmd` and `syn_post_cmd` could accept a list
of strings, such that:
syn_pre_cmd = [ "echo Command 1",
"echo Command 2" ]
Will produce this in the Makefile:
syn_pre_cmd:
echo Command 1
echo Command 2
Otherwise doing multiline commands is a bit ugly.https://ohwr.org/project/hdl-make/issues/60VHDL parser does not find all instances2019-02-12T09:35:17ZJoshua SmithVHDL parser does not find all instancesVHDL parser for finding instances/uses (dep USES) is not very robust.
Currently it is a regular expression defined as:
`"instance": "^ *(\w+) *\: *(\w+) *(port|generic) *map"`
This is essentially looking for an instance in the format:
`My_UUT : MyComponentName port/generic map ( ...`
However, instances can be created in many other ways including:
1. By `component` (with explicit `component` keyword),
2. By `entity` (with or without an architecture specified),
3. By `configuration`.
In each of these, I am pretty sure you can explicitly list the library
as well. Some examples:
`My_UUT : component mycomponent ....
My_UUT : entity mylibrary.myentityname
My_UUT : entity mylibrary.myentityname(myarchitecturename)
My_UUT : configuration mylibrary.myconfiguration`
I find it is most common to instanciate things by component, and entity.
Explicitly listing the library can aid in deconflicting common names,
and listing the architecture can deconflict the possibility of multiple
architectures associated with an entity.Javier D. Garcia-LasherasJavier D. Garcia-Lasherashttps://ohwr.org/project/hdl-make/issues/59VHDL instance not found when first in architecture2019-02-12T09:35:16ZJoshua SmithVHDL instance not found when first in architectureIf you have a VHDL architecture, with the first line being an instance,
I don't believe this is correctly found.
For example:
architecture my_arch ...
-- signals
begin
This_UUT_Not_Found : Unfound
port map ( ....
I believe this is because of the way the whitespace is removed from the
file, and lines are basically broken up by semicolons. In this case,
there is no semicolon after "begin" which makes the combined line after
whitespace removal look like this:
`begin This_UUT_Not_Found : Unfound port map ( ...`
This is a problem because the regular expression expects only spaces
before the instance, and not other characters (i.e. "^ \*")
I suspect this issue can be resolved by either:
1. Improving the algorithm which splits up code into lines, or
2. Making the VHDL regular expressions more forgiving of what precedes
the instance label.Javier D. Garcia-LasherasJavier D. Garcia-Lasherashttps://ohwr.org/project/hdl-make/issues/58VHDL parser does not correctly detect and remove character/string literals2019-02-12T09:35:15ZJoshua SmithVHDL parser does not correctly detect and remove character/string literalsThe VHDL parser does not robustly detect and remove character/string
literals. This affects both master, and 2014 far as I can see.
Currently, after removing comments, it searches for `"` or `'`
characters, and removes everything that is between them.
This does not account for use of VHDL attributes, like
`signalname'event, signalname'left, signalname'length` etc. A very
common occurrence of this is `clock'event`.
The algorithm for detecting a string literal must be improved to not
remove attributes (and all content thereafter, up to the next `"` or
`'`).
Interestingly enough, this problem affects the test case (`counter`),
but since there is not any "important" content after the `'event` in the
file, it does not show up as a problem.
architecture behv of counter is
signal Pre_Q: unsigned(7 downto 0);
begin
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= "00000000";
elsif (clock='1' and clock'event) then -- !! content parsing after this line will be incorrect !!
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
Q <= std_logic_vector(Pre_Q);
end behv;Javier D. Garcia-LasherasJavier D. Garcia-Lasheras