Hdlmake issueshttps://ohwr.org/project/hdl-make/issues2023-11-03T12:34:50Zhttps://ohwr.org/project/hdl-make/issues/122FEATURE: Adding library output in the "list-json" command2023-11-03T12:34:50ZRihards NovickisFEATURE: Adding library output in the "list-json" commandWe have found value in having libraries listed in the output of the `list-json` command as it eases integration with our scripts for continuous integration tests. I suppose, as a principle, any additional information in the `list-json` output could be helpful.
Here is a diff from the [develop](https://ohwr.org/project/hdl-make/tree/develop) branch, but if you add me to the project, I could make a proper merge request.
```diff
diff --git a/hdlmake/action/commands.py b/hdlmake/action/commands.py
index 9db2964..4aee79c 100644
--- a/hdlmake/action/commands.py
+++ b/hdlmake/action/commands.py
@@ -179,8 +179,9 @@ class Commands(Action):
lang='verilog'
else:
lang='unknown'
- print (' {{ "file": "{file}", "language": "{lang}"}}'.format(
- file=f.rel_path(cwd), lang=lang), end='')
+ print (' {{ "file": "{file}", "language": "{lang}", "library": "{library}"}}'.format(
+ file=f.rel_path(cwd), lang=lang, library=f.library), end='')
+
print()
print(' ]')
print('}')
```https://ohwr.org/project/hdl-make/issues/121Quartus: set_parameter?2023-05-26T09:02:09ZTom LevensQuartus: set_parameter?There seems to be no way to add `set_parameter` assignments in the Quartus project.
Note the `syn_properties` attribute maps to `set_global_assignment`.https://ohwr.org/project/hdl-make/issues/118fetchto variable should be converted to an absolute path2022-12-05T16:17:00ZDimitris Lampridisfetchto variable should be converted to an absolute pathThe `fetchto` variable declared at the top-level Manifest should be converted to an absolute path, before it is passed on to child Manifests, otherwise the relative path will probably not be valid unless the child Manifest is at the same folder level as the top-level one.https://ohwr.org/project/hdl-make/issues/104Dependency parser and vhd files2020-01-23T16:32:57ZA. HahnDependency parser and vhd filesHi,
[Quartus user here:] Is there a way to force .vhd files to end up inside my .qsf (Quartus project) file?
Already tried extra_modules, does not work for me.
hdlmake version: 3.0https://ohwr.org/project/hdl-make/issues/99Xilinx ISE: make project fails if project file exists2019-09-11T11:21:54ZDimitris LampridisXilinx ISE: make project fails if project file existsin Xilinx ISE, if the project file already exists, the `make project` target fails with:
```
ERROR:TclTasksC:project_087: Project file "my_project.xise" already exists. Use [project open "my_project.xise"] instead.
```
Obviously, we should check against this and either open the project and edit it, or delete it and start from scratch.https://ohwr.org/project/hdl-make/issues/98Cannot simulate or synthesize if I have multiple vhdl files2019-08-15T09:31:52ZKarthik SelvanCannot simulate or synthesize if I have multiple vhdl filesCan I use the following in each of my VHDL files and instantiate them without defining components in any of my VHDL files?
library work;
use work.all;
![Screenshot_20190815_112902](/uploads/6e1fb53dacffb38fb50b78939fca71fa/Screenshot_20190815_112902.png)
![Screenshot_20190815_113146](/uploads/8a65fa265cac5020e4bffc764a8438f9/Screenshot_20190815_113146.png)https://ohwr.org/project/hdl-make/issues/96DISCUSSION: Find the best way to support 'attirbutes' kind for modules or files2019-06-04T13:31:08ZNicolas ChevillotDISCUSSION: Find the best way to support 'attirbutes' kind for modules or filesIn LATOME project, hdl-make has been enhanced with the possibility to add attributes to files or modules in Manifests.
The following attributes are added:
* action: uses the module/file only if the action matches
* dependencies: add fixed dependencies to a file, in order for example to compile Intel Quartus files (220model.v/20pack.vhd/altera_mf.v...) in the proper order as some of those files are encrypted and cannot therefore be checked with the VHDL/Verilog parser
* enable: uses the module/file only if the condition is True
* library: overrides the default library for the file. Useful for example to compile Intel Quartus files as they must be compiled in various libraries such that 1 Manifest only is used instead of 1 per library
* preprocess: used to preprocess the file, either replace an environment variable by its content (to have generic code) or calls C-preprocessor to use #if #else #endif constructs
* relations: to generate relation files locally to the Manifest for example if a module is common to many others and does not change like intel Quartus EDA files
* vcom_opt: allows to add a specific VHDL compiler option to the file
Example Manifest.py extracted from LATOME project:
```
# List of modules
modules = {
'local': [
'user_src',
'$REPOSITORY_ROOT_PATH/PoC',
'$REPOSITORY_ROOT_PATH/LATOME/src/ipctrl/src/ipctrl_util',
{'$REPOSITORY_ROOT_PATH/LATOME/src/pattern_generator': {'enable': 'PATTERN_GENERATOR_INTERNAL_ENABLE'}},
],
}
# Default library
library = 'istage'
# List of source files
files = [
{'istage_arch.vhd': {'preprocess': 'cpp'}},
'istage_comp.vhd',
'istage_ent.vhd',
]
```
This implementation is a choice. Other implementations can be made. Let's discuss on the best way to implement it.Tristan GingoldTristan Gingoldhttps://ohwr.org/project/hdl-make/issues/95DISCUSSION: getting rid of parsers (and automatic dependencies)2023-01-12T17:38:24ZTristan GingoldDISCUSSION: getting rid of parsers (and automatic dependencies)I think HDLmake should get rid of the automatic computation of dependencies.
The main reason is that the parsers (which are based on regexp) are buggy and incomplete. You could reply: 'just fix them'. But no. This is not that simple. Fixing the parsers means writing full vhdl and systemverilog parsers. That's a lot of work. We could rely on external parsers, but there is no such parser in Python, so the installation would be more complex. And we need mixed vhdl/verilog dependencies.
Even with the best parsers we have to deal with encrypted modules...
Without the automatic dependencies, the behaviour would be like `hdlmake -a`. To ease the adoption of this new behaviour, we need to add some features. In particular, importing only some Manifest files from a module (and not only the top-level one).
Comments are welcome.Tristan GingoldTristan Gingoldhttps://ohwr.org/project/hdl-make/issues/94Allow absolute paths in manifests2019-05-01T07:43:49ZNicolas ChevillotAllow absolute paths in manifestsIn order to simulate IPs from Altera for example, it is needed to compile code that is available in the Quartus software distribution. For example:
```
$HDLMAKE_QUARTUS_PATH/../eda/sim_lib/220model.v
```
This will be an absolute path as it does not belong to the project being compiled. Therefore the tool should allow such paths.Nicolas ChevillotNicolas Chevillothttps://ohwr.org/project/hdl-make/issues/93Expand environment variables in module/files paths2019-06-03T06:57:49ZNicolas ChevillotExpand environment variables in module/files pathsPaths pointing to Quartus toolchain or even files from a common location might be pointed to by environment variables.
For example in one Manifest.py:
```
modules = {
'local': [
'$PROJECT_ROOT_PATH/src/fpga/testbench',
],
}
```
os.path.expandvars function can be used to exapnd it.Nicolas ChevillotNicolas Chevillothttps://ohwr.org/project/hdl-make/issues/34Parameter is misinterprated and misinterpreted as (missing) module2019-03-30T02:35:05ZAndreas Bergmann (Consult)Parameter is misinterprated and misinterpreted as (missing) moduleThe following RAM simulation module uses a predefined parameter, which
is later used for defining a delay.
LINE 46: Tsa
used in Line 67 \#Tsa
This construct seems to be misinterprated as a (missing hdl-module).
This is just a WARNING in scriptoutput and it seems to work fine. Anyway
its a little bit uggly.
### Files
* [IS61LV6416L.v](/uploads/cbfa8069b088b9cd325add200ade41c3/IS61LV6416L.v)
* [simple.v](/uploads/4e83d9a1d057d32bc766cd3e5ee2f0bf/simple.v)https://ohwr.org/project/hdl-make/issues/20Relations missing for VHDL package to be used in system verilog2019-02-12T09:34:56ZNicolas ChevillotRelations missing for VHDL package to be used in system verilogIn case of mixed-language simulation, a VHDL file defining a package
(library test, package this\_package) generates the following relation:
Provide package test.this\_package
If we want to use this package from SystemVerilog file, we need to use
the following import:
import this\_package::\*;
and compile the SystemVerilog file using -L test to include the test
library.
However the Verilog parser in this case will generate the following
relation: Use package this\_package
Therefore the dependency is not found.
The VHDL parser should in case of defining a package add the followinfg
2 relations:
Provide package test.this\_package
Provide package this\_package
so the dependency will be fulfilledJavier D. Garcia-LasherasJavier D. Garcia-Lasherashttps://ohwr.org/project/hdl-make/issues/17String Element inside $display Verilog function will be misinterpreted as module2019-03-30T02:35:25ZAndreas BergmannString Element inside $display Verilog function will be misinterpreted as moduleInside verilog module, inside a $display function; the first string
element will be misinterpreted as (unresolved) Module:
WARNING new\_dep\_solver.py:91: solve() Relation Use module
'work.nomodule' in ps2mouse.v not satisfied by any source file
module ps2module ();
task configure;
begin
$display("NoModule dontmatter (0xff)");
end
endtask
endmodule
### Files
* [ps2mouse.v](/uploads/6242bec162a2d490cdf41a10b9dae940/ps2mouse.v)https://ohwr.org/project/hdl-make/issues/13multitline signal declaration generates wrong relations in VHDL2019-02-12T09:34:53ZNicolas Chevillotmultitline signal declaration generates wrong relations in VHDLfollowing VHDL code:
\-------
signal sig1, sig2,
sig3: std\_logic;
\-------
will generate a "use","module","std\_logic" relation.
I suggest that the VHDL is preprocessed this way:
1\) remove all comments
2\) put everything on a single line
3\) cut lines after each semicolon (optional)
this way the above piece of code does not generate a wrong relationhttps://ohwr.org/project/hdl-make/issues/12VHDL parser should create relations for package without library2019-03-30T20:41:05ZNicolas ChevillotVHDL parser should create relations for package without libraryIn order to be able to work with both VHDL and SystemVerilog, the VHDL
parser should not only create a package relation in the form of:
\["Provide", "package", "<library_name>.<package_name>"\],
but also
\["Provide", "package", "<package_name>"\],
I only found the following way to use a VHDL package from SV:
import <package_name>::\*;
this does not include the library where this package is defined.