VHDL parser does not find all instances
VHDL parser for finding instances/uses (dep USES) is not very robust.
Currently it is a regular expression defined as:
"instance": "^ *(\w+) *\: *(\w+) *(port|generic) *map"
This is essentially looking for an instance in the format:
My_UUT : MyComponentName port/generic map ( ...
However, instances can be created in many other ways including:
entity(with or without an architecture specified),
In each of these, I am pretty sure you can explicitly list the library as well. Some examples:
My_UUT : component mycomponent .... My_UUT : entity mylibrary.myentityname My_UUT : entity mylibrary.myentityname(myarchitecturename) My_UUT : configuration mylibrary.myconfiguration
I find it is most common to instanciate things by component, and entity. Explicitly listing the library can aid in deconflicting common names, and listing the architecture can deconflict the possibility of multiple architectures associated with an entity.