Hdlmake vsim & xsim targets compile verilog headers as separate files.
I have a testbench consisting of a single 'main.sv' file which includes several SystemVerilog header files. hdlmake attempts to compile each header as an independent design unit (calling vlog/xvlog on each included file found), causing errors.
-- top simulation manifest below --
sim_tool = "modelsim"
top_module="main"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
sim_top="main"
syn_device="xc6slx150t"
include_dirs=["../include/wb", "../include" ]
files = [ "main.sv" ]
modules = { "local" : [ "../../top/spec" ] }