include_dirs does not seem to work for synthesis
I have SystemVerilog project that uses an include to define some constants. Due to the BI VFC project structure, the include file is not in the same directory as the top level source.
I have added the include_dirs = ["../modules"]
directive to my Manifest.py, but I still get the following errors:
INFO action.py:169: build_file_set() Detected 7 supported files that are not parseable
INFO action.py:172: build_file_set() Detected 347 supported files that can be parsed
ERROR vlog_parser.py:270: do_expand() No expansion for macro '`SYS_CLK_FREQ' (localparam c_ClkFrequency = `SYS_CLK_FREQ;) (/afs/cern.ch/work/t/tlevens/repos/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VfcHdSystem.sv)
ERROR vlog_parser.py:123: _search_include() Can't find VfcHdConfig.vh for /afs/cern.ch/work/t/tlevens/repos/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VfcHdTop.sv in any of the include directories: ../../libs/VFC-HD_System/hdl/modules
Exiting
It looks like the include_dirs
is not being taken into account when parsing the files.