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Not fetching to the right dir
#69
· opened
Dec 10, 2012
by
Projects
feature
CLOSED
1
updated
Feb 12, 2019
Create package (binaries only and source only)
#68
· opened
Aug 05, 2013
by
Benoit Rat
feature
CLOSED
1
updated
Mar 31, 2019
Wrong help message
#67
· opened
Jan 31, 2014
by
Projects
feature
CLOSED
1
updated
Feb 12, 2019
list-mods command throwing TypeError
#66
· opened
Jan 31, 2014
by
Projects
feature
CLOSED
3
updated
Feb 12, 2019
Incorporate way of handling Xilinx Coregen ( *.xco ) components
#65
· opened
Apr 30, 2014
by
David Cussans
CLOSED
3
updated
Mar 29, 2019
XISE: properties from manifest
#64
· opened
May 21, 2014
by
Tom Levens
CLOSED
3
updated
Mar 29, 2019
ISE: Files missing from make clean
#63
· opened
May 21, 2014
by
Tom Levens
CLOSED
0
updated
Feb 12, 2019
syn_post_cmd not run by make
#62
· opened
May 21, 2014
by
Tom Levens
CLOSED
0
updated
Feb 12, 2019
syn_*_cmd multiline
#61
· opened
May 21, 2014
by
Tom Levens
CLOSED
2
updated
Feb 12, 2019
VHDL parser does not find all instances
#60
· opened
Sep 27, 2014
by
Joshua Smith
feature
CLOSED
2
updated
Feb 12, 2019
VHDL instance not found when first in architecture
#59
· opened
Sep 27, 2014
by
Joshua Smith
bug
CLOSED
1
updated
Feb 12, 2019
VHDL parser does not correctly detect and remove character/string literals
#58
· opened
Sep 27, 2014
by
Joshua Smith
bug
CLOSED
1
updated
Feb 12, 2019
no attribute 'parse' for '.vo' files
#57
· opened
Oct 02, 2014
by
Adrian Fiergolski
bug
CLOSED
0
updated
Feb 12, 2019
imported packages are not added in dependencies for SystemVerilog files
#56
· opened
Oct 03, 2014
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
libraries used in vhdl files are not added to dependencies
#55
· opened
Nov 05, 2014
by
Adrian Fiergolski
bug
CLOSED
2
updated
Mar 29, 2019
instantiation without component declaration (VHDL)
#54
· opened
Nov 05, 2014
by
Adrian Fiergolski
bug
CLOSED
0
updated
Feb 12, 2019
VHDL: case sensitiveness
#53
· opened
Nov 05, 2014
by
Adrian Fiergolski
bug
CLOSED
0
updated
Feb 12, 2019
circular dependenceis
#52
· opened
Nov 07, 2014
by
Adrian Fiergolski
bug
CLOSED
0
updated
Feb 12, 2019
VHDL: conent of generate
#51
· opened
Nov 07, 2014
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
library support
#50
· opened
Nov 10, 2014
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
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