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The information about "circular[...] dependency dropped" is neither error nor warning
#28
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
Hdlmake includes the target file when generating a simulation Makefile
#27
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
List-files doesn't generate the parsed dependency-driven fileset
#26
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
2
updated
Mar 29, 2019
Imporve submodules & fetch behavior
#25
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
1
updated
Mar 29, 2019
Emit a warning when fetch doesn't points to a specific repository commit or tag
#24
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
1
updated
Mar 30, 2019
Improve SDB integration and workflow
#23
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
1
updated
Mar 31, 2019
Support for skipping encoded system verilog files
#22
· opened
May 31, 2016
by
Nicolas Chevillot
feature
CLOSED
2
updated
Mar 29, 2019
Quit upon error should generate an error code different than 0
#21
· opened
May 31, 2016
by
Nicolas Chevillot
bug
CLOSED
1
updated
Mar 30, 2019
Rare Labeling in Verilig causes Warning of non-existing dependencies
#19
· opened
Jun 02, 2016
by
Andreas Bergmann (Consult)
CLOSED
1
updated
Mar 29, 2019
modules export tool with lightweight GUI
#18
· opened
Jun 02, 2016
by
Grzegorz Daniluk
feature
CLOSED
2
updated
Mar 31, 2019
Flatten option for Fetch doesn't work
#16
· opened
Jul 22, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Do not fetch submodules recursively
#15
· opened
Jul 22, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Assign a name for the Web-based frontend plugin.
#14
· opened
Sep 19, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
1
updated
Mar 30, 2019
isim tool and mixed language code
#11
· opened
Jul 17, 2017
by
Karol Krizka
CLOSED
1
updated
Mar 29, 2019
[SV + UVM]: Could not find a top level file
#10
· opened
Jan 26, 2018
by
Adrian Fiergolski
bug
CLOSED
1
updated
Mar 30, 2019
[SV + UVM]: modelsim and +incdir+
#9
· opened
Jan 30, 2018
by
Adrian Fiergolski
bug
CLOSED
2
updated
Mar 30, 2019
Hdlmake vsim & xsim targets compile verilog headers as separate files.
#8
· opened
Feb 03, 2018
by
Tomasz Wlostowski
bug
CLOSED
2
updated
Mar 29, 2019
Active-HDL not working
#7
· opened
Mar 14, 2018
by
Jan L.
CLOSED
1
updated
Mar 30, 2019
Test of Active-HDL failes under CMD
#6
· opened
Mar 14, 2018
by
Jan L.
CLOSED
1
updated
Mar 30, 2019
Incorrect source file handling in Diamond (and Libero)
#5
· opened
Mar 14, 2018
by
Jan L.
CLOSED
1
updated
Mar 30, 2019
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