Project description
The goal of the project is to provide HDL developers with tools, whose aim is to solve typical problems connected with simulation and synthesis.
Simulation
For the time being we are attached to Modelsim as the best tool for HDL simulation. All of the scripts are intended to use this tool.
When compiling VHDL files for simulation, one must ensure their correct
order. In every project there is a dependency tree among files - one
file makes use of data from an other file by e.g. including it. Each
file may not be compiled until all files it is dependent on are
compiled, otherwise the compilation process will fail. There are no
major obstacles when simulating Xilinx projects. The Project Navigator
can automatically generate a bash script using Modelsim for any project.
The script ensures correct compilation order and that all dependencies
will be met.
For Altera there is no tool for this purpose delivered by the vendor.