New Features
Below is a list of new features added to HDLmake recently by Pawel - these features are in the master branch.
| N | Name | Description | Status | Tester | Test Results | Issues/Comments |
|---|---|---|---|---|---|---|
| 1 | Better HDLMAKE_COREDIR handling | Add an option to select between the HDLMAKE_COREDIR and URLs provided in the manifests. | probably done/to be tested | |||
| 2 | Better module listing | Add an option to show where each module comes from. | done/To be tested | |||
| 3 | Git submodule support | self-explanatory | done/to be tested | |||
| 4 | Integrate full VHDL dependency generator | done/to be tested | Tom | |||
| 5 | Make a unified makefile for local and remote synthesis | done/to be tested | ||||
| 6 | Screen support for remote synthesis. | make remotewill open a screen session on the synthesis machine.make restorewill restore the screen session with the running synthesis.make syncwill copy results of last synthesis back to the local machine.make terminate` will immediately stop the synthesis of the project |
done (works differently than intended)/to be tested | Thedi | ||
| 7 | Add option for checking the environment setup. | done/to be tested | Tom | |||
| 8 | Add option to specify version of tools to be used. | done/to be tested | ||||
| 9 | Fetch modules to a single directory, whatever the structure of the project is. | probably done/to be tested | Thedi | |||
| 10 | Clean-up the source code. | done | ||||
| 11 | Move features from ISYP branch to master branch. | done/to be tested | ||||
| 12 | Clean-up environmental variables and improve help. | done/to be tested | Thedi | |||
| 13 | Clean-up command line options. | done/to be tested | ||||
| 14 | Improve --merge-cores to dump revision and date of eash subfile in the merged output. | done/to be tested | Tom | |||
| 15 | Fix all OHWR issues | see https://www.ohwr.org/project/hdl-make/issues | done/to be tested | Thedi | ||
| 16 | Update information in *.xise project once the device in the manifest gets changed. | done/to be tested | ||||
| 17 | Integrate ISim support written by Lucas Russo | done/to be tested | ||||
| 18 | Add Verilog include path as a manifest parameter. | done/to be tested | ||||
| 19 | Add finer control for synthesis stages | It will be allowed to choose between synthesis/MAP/PAR stages to be re-run. | not done | |||
| 20 | Arrange a separate repository with test projects | not done | ||||
| 21 | Add support for Windows OS | self-explanatory | not done, but code-base prepared to be windows-friendly | Tom | ||
| 22 | No binary in repo | Excluded the hdlmake binary from the repository. The git repository contains the development version and no executable file will be held there. The stable versions will become releases and will be available to download from the project page (https://www.ohwr.org/project/hdl-make/wikis/Documents/Project-Attachments). | When the master is approved, binary with stable versions will be uploaded |