Commit 2f031cf3 authored by David Cussans's avatar David Cussans

Connected trigger output to GPIO pin

parent fd606682
{ Machine generated file created by SPI }
{ Last modified was 12:44:26 Thursday, January 07, 2016 }
{ Last modified was 18:39:41 Friday, September 16, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -34,7 +34,6 @@ HPF_SPEC_PLOT_PAGESIZE 'YES'
HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc049a_toplevel1.ps'
SEARCH_HISTORY 'c38' 'c32' 'c75' 'c85' 'c94'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '9'
......@@ -45,6 +44,7 @@ HPF_PLOT_PAGESIZE 'A4'
HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4'
HPF_SCALEFACTOR '0.000000'
SEARCH_HISTORY 'R8' 'c38' 'c32' 'c75' 'c85'
END_CONCEPTHDL
START_PKGRXL
......@@ -103,15 +103,8 @@ retain_existing_xnets_and_diffpairs 'NO'
END_ECSET_MODELS
START_VARIANT
last_variant_file 'variant.dat'
last_edit_type '2'
last_sorted_column 'REFDES'
pref_status_name 'Pref'
sort_style '0'
annotation_property_name 'VARIANT'
annotation_property_value '*'
annotation_DNIproperty_value 'DNI'
columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER'
last_variant_file 'variant.dat'
END_VARIANT
START_ALLEGRO
......
\t (00:00:04) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:04) Journal start - Thu Apr 14 13:23:40 2016
\t (00:00:04) Host=voltar.phy.bris.ac.uk User=phdgc Pid=3926 CPUs=8
\t (00:00:04) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/pc049a_lemo_db.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr7061 -mpshost voltar.phy.bris.ac.uk
\t (00:00:04)
\t (00:00:05) Opening existing design...
\d (00:00:05) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_4l_13.brd
\t (00:00:06) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:00:06) trapsize 4725
\i (00:00:06) trapsize 4605
\i (00:00:07) trapsize 4745
\i (00:00:07) trapsize 3996
\t (00:00:07) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:00:07) trapsize 3996
\i (00:00:08) ifp
\i (00:00:11) zoom fit
\t (00:00:11) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:00:11) trapsize 10169
\i (00:01:41) pick grid 3.4574 -44.2338
\t (00:01:41) last pick: 3.5000 -44.2000
\i (00:01:49) plctxt out
\i (00:02:01) setwindow form.plctxt
\i (00:02:01) FORM plctxt filename placement_pin1.txt
\i (00:02:01) FORM plctxt pin_1 YES
\i (00:02:03) FORM plctxt execute
\t (00:02:03) Starting Place symbols by text file...
\i (00:03:00) FORM plctxt cancel
\i (00:03:01) setwindow pcb
\i (00:03:01) ifp
\i (00:08:23) zoom points
\t (00:08:23) Pick 1st corner of the new window.
\i (00:08:24) pick -39.0477 18.4053
\t (00:08:24) last pick: -39.0477 18.4053
\t (00:08:24) Pick to complete the window.
\i (00:08:25) pick 36.6072 -12.3041
\t (00:08:25) last pick: 36.6072 -12.3041
\t (00:08:25) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:08:25) trapsize 2765
\i (00:08:25) ifp
\i (00:08:47) pick grid -5.1468 -15.7168
\t (00:08:47) last pick: -5.1000 -15.7000
\i (00:08:48) roam y 96
\i (00:08:48) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:50) roam y -96
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\i (00:08:50) roam y -96
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\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:52) roam x -96
\i (00:08:52) roam x -96
\i (00:08:54) show element
\i (00:11:26) pick grid -57.0313 -82.5654
\t (00:11:26) last pick: -57.0000 -82.6000
\i (00:11:28) zoom out
\i (00:11:28) setwindow pcb
\i (00:11:28) zoom out -70.2487 -91.3033
\t (00:11:28) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (00:11:28) trapsize 5530
\i (00:11:29) zoom out
\i (00:11:29) setwindow pcb
\i (00:11:29) zoom out -70.2488 -91.3034
\t (00:11:29) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:11:29) trapsize 11061
\i (00:11:29) zoom out
\i (00:11:29) setwindow pcb
\i (00:11:29) zoom out -70.2487 -91.3033
\t (00:11:29) Grids are drawn 3.2000, 3.2000 apart for enhanced viewability.
\i (00:11:29) trapsize 22121
\i (00:11:45) show element
\i (00:11:50) setwindow form.find
\i (00:11:50) FORM find shapes YES
\i (00:11:52) setwindow pcb
\i (00:11:52) pick grid -88.6647 4.0949
\t (00:11:52) last pick: -88.7000 4.1000
\i (00:15:10) odb_out
\i (00:15:18) fillin no
(00:15:18) Loading mfg.cxt
\i (00:15:31) exit
\e (00:15:32) Do you want to save the changes you made to pc049a_lemo_db_4l_13.brd?
\i (00:15:35) fillin no
\t (00:15:38) Journal end - Thu Apr 14 13:39:13 2016
\t (00:00:51) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:51) Journal start - Thu Apr 14 12:38:47 2016
\t (00:00:51) Host=voltar.phy.bris.ac.uk User=phdgc Pid=1851 CPUs=8
\t (00:00:51) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/pc049a_lemo_daughter_board.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr7061 -mpshost voltar.phy.bris.ac.uk
\t (00:00:51)
\d (00:00:51) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_4l_13.brd
\i (00:00:51) ifp
\i (00:00:54) zoom fit
\t (00:00:54) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:00:54) trapsize 10169
\i (00:43:42) trapsize 13752
\i (00:44:11) exit
\t (00:44:12) Journal end - Thu Apr 14 13:22:07 2016
\t (00:00:04) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:04) Journal start - Thu Apr 14 13:23:40 2016
\t (00:00:04) Host=voltar.phy.bris.ac.uk User=phdgc Pid=3926 CPUs=8
\t (00:00:04) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/pc049a_lemo_db.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr7061 -mpshost voltar.phy.bris.ac.uk
\t (00:00:04)
\t (00:00:05) Opening existing design...
\d (00:00:05) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_4l_13.brd
\t (00:00:06) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:00:06) trapsize 4725
\i (00:00:06) trapsize 4605
\i (00:00:07) trapsize 4745
\i (00:00:07) trapsize 3996
\t (00:00:07) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:00:07) trapsize 3996
\i (00:00:08) ifp
\i (00:00:11) zoom fit
\t (00:00:11) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:00:11) trapsize 10169
\i (00:01:41) pick grid 3.4574 -44.2338
\t (00:01:41) last pick: 3.5000 -44.2000
\i (00:01:49) plctxt out
\i (00:02:01) setwindow form.plctxt
\i (00:02:01) FORM plctxt filename placement_pin1.txt
\i (00:02:01) FORM plctxt pin_1 YES
\i (00:02:03) FORM plctxt execute
\t (00:02:03) Starting Place symbols by text file...
\i (00:03:00) FORM plctxt cancel
\i (00:03:01) setwindow pcb
\i (00:03:01) ifp
\i (00:08:23) zoom points
\t (00:08:23) Pick 1st corner of the new window.
\i (00:08:24) pick -39.0477 18.4053
\t (00:08:24) last pick: -39.0477 18.4053
\t (00:08:24) Pick to complete the window.
\i (00:08:25) pick 36.6072 -12.3041
\t (00:08:25) last pick: 36.6072 -12.3041
\t (00:08:25) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:08:25) trapsize 2765
\i (00:08:25) ifp
\i (00:08:47) pick grid -5.1468 -15.7168
\t (00:08:47) last pick: -5.1000 -15.7000
\i (00:08:48) roam y 96
\i (00:08:48) roam y 96
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\i (00:08:50) roam y -96
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\i (00:08:51) roam x -96
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\i (00:08:51) roam x -96
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\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:52) roam x -96
\i (00:08:52) roam x -96
\i (00:08:54) show element
\i (00:11:26) pick grid -57.0313 -82.5654
\t (00:11:26) last pick: -57.0000 -82.6000
\i (00:11:28) zoom out
\i (00:11:28) setwindow pcb
\i (00:11:28) zoom out -70.2487 -91.3033
\t (00:11:28) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (00:11:28) trapsize 5530
\i (00:11:29) zoom out
\i (00:11:29) setwindow pcb
\i (00:11:29) zoom out -70.2488 -91.3034
\t (00:11:29) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:11:29) trapsize 11061
\i (00:11:29) zoom out
\i (00:11:29) setwindow pcb
\i (00:11:29) zoom out -70.2487 -91.3033
\t (00:11:29) Grids are drawn 3.2000, 3.2000 apart for enhanced viewability.
\i (00:11:29) trapsize 22121
\i (00:11:45) show element
\i (00:11:50) setwindow form.find
\i (00:11:50) FORM find shapes YES
\i (00:11:52) setwindow pcb
\i (00:11:52) pick grid -88.6647 4.0949
\t (00:11:52) last pick: -88.7000 4.1000
\i (00:15:10) odb_out
\i (00:15:18) fillin no
(00:15:18) Loading mfg.cxt
\i (00:15:31) exit
\e (00:15:32) Do you want to save the changes you made to pc049a_lemo_db_4l_13.brd?
\i (00:15:35) fillin no
\t (00:15:38) Journal end - Thu Apr 14 13:39:13 2016
\t (46:40:47) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (46:40:47) Journal start - Thu Feb 18 12:00:53 2016
\t (46:40:47) Host=fortis.phy.bris.ac.uk User=phdgc Pid=27642 CPUs=4
\t (46:40:47) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055//tools/pcb/bin/allegro.exe
\t (46:40:47)
\d (46:40:47) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/physical/pc049a_toplevel_52.brd
\i (46:40:47) ifp
\i (46:40:56) opencd /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_12.brd
\t (46:40:57) Opening existing design...
\t (46:40:57) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (46:40:57) trapsize 7128
\t (46:40:57) Journal end - Thu Feb 18 12:01:03 2016
\t (00:00:03) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:03) Journal start - Fri Sep 16 12:54:12 2016
\t (00:00:03) Host=fortis.phy.bris.ac.uk User=phdgc Pid=7639 CPUs=4
\t (00:00:03) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/design_files/pc049a_toplevel.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr29900 -mpshost fortis.phy.bris.ac.uk
\t (00:00:03)
\t (00:00:04) Opening existing design...
\d (00:00:04) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/design_files/worklib/pc049a_toplevel/physical/pc049a_toplevel_52.brd
\i (00:00:04) trapsize 17320
\i (00:00:04) trapsize 17755
\i (00:00:05) trapsize 15373
\i (00:00:05) trapsize 15373
\i (00:00:05) etchedit
\i (00:00:10) setwindow form.find
\i (00:00:10) FORM find name_type Net
\i (00:00:11) FORM find find_by_name
\i (00:00:17) setwindow form.findname
\i (00:00:17) FORM findname namefilter p1v2*
\i (00:00:18) FORM findname objlist P1v2
\i (00:00:20) FORM findname select
\i (00:00:20) setwindow pcb
\i (00:00:20) trapsize 1971
\i (00:00:24) prepopup 32.3248 89.9984
\i (00:00:26) pick grid 30.4327 87.6726
\t (00:00:26) last pick: 30.4300 87.6700
\i (00:00:28) pick grid 24.0467 94.2162
\t (00:00:28) last pick: 24.0500 94.2200
\i (00:00:36) zoom out
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom out 44.1506 93.7826
\i (00:00:36) trapsize 3942
\i (00:00:59) pick grid 23.8102 93.9403
\t (00:00:59) last pick: 23.8100 93.9400
\i (00:01:13) pick grid 19.8683 104.5047
\t (00:01:13) last pick: 19.8700 104.5000
\i (00:02:28) xNet P3v3
\i (00:02:28) xname_flush
\i (00:02:28) trapsize 13737
\i (00:03:45) setwindow form.findname
\i (00:03:45) FORM findname namefilter p3v3
\i (00:03:47) FORM findname objlist P3v3
\i (00:03:48) FORM findname destlist P1V2
\i (00:03:50) FORM findname select
\i (00:03:50) setwindow pcb
\i (00:03:50) trapsize 13737
\i (00:03:56) zoom in
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom in 43.0696 70.6481
\i (00:03:56) trapsize 6868
\i (00:03:56) zoom in
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom in 43.0696 70.6481
\i (00:03:56) trapsize 3434
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:04:04) pick grid 12.5736 104.4927
\t (00:04:04) last pick: 12.5700 104.4900
\i (00:05:04) setwindow form.findname
\i (00:05:04) FORM findname objtype Symbol (or Pin)
\i (00:05:07) FORM findname namefilter lk1
\i (00:05:09) FORM findname objlist Lk1
\i (00:05:10) FORM findname select
\i (00:05:10) setwindow pcb
\i (00:05:10) trapsize 490
\i (00:05:12) zoom out
\i (00:05:12) setwindow pcb
\i (00:05:12) zoom out 59.2736 20.5242
\i (00:05:12) trapsize 980
\i (00:05:37) setwindow form.findname
\i (00:05:37) FORM findname namefilter p3v3
\i (00:05:40) FORM findname objtype Net
\i (00:05:41) FORM findname objlist P3v3
\i (00:05:42) FORM findname select
\i (00:05:42) setwindow pcb
\i (00:05:42) trapsize 13737
\i (00:05:44) zoom points
\t (00:05:44) Pick 1st corner of the new window.
\i (00:05:45) pick -2.2625 117.3538
\t (00:05:45) last pick: -2.2625 117.3538
\t (00:05:45) Pick to complete the window.
\i (00:05:46) pick 39.4979 82.1871
\t (00:05:46) last pick: 39.4979 82.1871
\i (00:05:46) trapsize 2290
\i (00:05:46) etchedit
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:24) roam y 96
\i (00:06:24) roam y 96
\i (00:06:24) roam y 96
\i (00:06:24) roam y 96
\i (00:06:24) roam x 96
\i (00:06:24) roam x 96
\i (00:06:25) roam x 96
\i (00:06:25) roam x 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:27) roam y 96
\i (00:06:27) roam y 96
\i (00:06:27) roam y 96
\i (00:06:27) roam y 96
\i (00:15:02) setwindow form.find
\i (00:15:02) FORM find find_name P4V6
\i (00:15:02) setwindow pcb
\i (00:15:02) trapsize 1660
\i (00:15:08) zoom out
\i (00:15:08) setwindow pcb
\i (00:15:08) zoom out 65.8556 6.8565
\i (00:15:08) trapsize 3319
\i (00:22:54) setwindow form.vf_vis
\i (00:22:54) FORM vf_vis 10 all_colorvisible YES
\i (00:23:04) setwindow form.find
\i (00:23:04) FORM find symbols YES
\i (00:23:10) setwindow pcb
\i (00:23:10) prepopup 103.0290 14.2912
\i (00:23:11) pick grid 104.6221 17.8094
\t (00:23:11) last pick: 104.6200 17.8100
\i (00:23:12) show element
\i (00:23:15) setwindow form.find
\i (00:23:15) FORM find symbols YES
\i (00:23:40) setwindow pcb
\i (00:23:40) xrefdes R8.2
\i (00:23:40) xname_flush
\i (00:23:40) trapsize 182
\i (00:23:49) zoom out
\i (00:23:49) setwindow pcb
\i (00:23:49) zoom out 75.2600 -1.3036
\i (00:23:49) trapsize 364
\i (05:39:55) exit
\e (05:39:55) Do you want to save the changes you made to pc049a_toplevel_52.brd?
\i (05:39:58) fillin no
\t (05:39:59) Journal end - Fri Sep 16 18:34:08 2016
\t (00:00:05) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:05) Journal start - Tue Feb 2 17:46:55 2016
\t (00:00:05) Host=fortis.phy.bris.ac.uk User=phdgc Pid=3330 CPUs=4
\t (00:00:05) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055//tools/pcb/bin/allegro.exe
\t (00:00:05) Journal start - Fri Sep 16 12:48:07 2016
\t (00:00:05) Host=fortis.phy.bris.ac.uk User=phdgc Pid=7399 CPUs=4
\t (00:00:05) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055//tools/pcb/bin/allegro.exe pc049a_toplevel_52.brd
\t (00:00:05)
\t (00:00:07) Opening existing design...
\d (00:00:07) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/physical/pc049a_toplevel_52.brd
\i (00:00:08) trapsize 20270
\i (00:00:08) trapsize 19784
\i (00:00:08) trapsize 20354
\i (00:00:08) trapsize 17283
\i (00:00:08) trapsize 17283
\i (00:00:09) ifp
\i (00:00:11) open
\i (00:00:23) fillin "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc050a/trunk/design_files/worklib/pc050a_clock_board_40mhz/physical/pc050a_clock_board_40mhz_08.brd"
\i (00:00:23) cd "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc050a/trunk/design_files/worklib/pc050a_clock_board_40mhz/physical"
\t (00:00:23) Opening existing design...
\t (00:00:23) Grids are drawn 0.6400, 0.6400 apart for enhanced viewability.
\i (00:00:23) trapsize 4754
\t (00:00:23) Journal end - Tue Feb 2 17:47:13 2016
\d (00:00:07) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/design_files/worklib/pc049a_toplevel/physical/pc049a_toplevel_52.brd
\i (00:00:07) trapsize 17320
\i (00:00:07) trapsize 17755
\i (00:00:08) trapsize 15373
\i (00:00:08) trapsize 15373
\i (00:00:09) etchedit
\i (00:00:12) zoom points
\t (00:00:12) Pick 1st corner of the new window.
\i (00:00:13) pick 7.7680 119.6919
\t (00:00:13) last pick: 7.7680 119.6919
\t (00:00:13) Pick to complete the window.
\i (00:00:13) pick 36.3611 85.2573
\t (00:00:13) last pick: 36.3611 85.2573
\i (00:00:13) trapsize 2185
\i (00:00:13) etchedit
\i (00:00:16) show element
\i (00:00:19) setwindow form.find
\i (00:00:19) FORM find all_off
\i (00:00:20) FORM find pins YES
\i (00:01:10) setwindow pcb
\i (00:01:10) trapsize 2457
\i (00:01:51) exit
\e (00:01:51) Do you want to save the changes you made to pc049a_toplevel_52.brd?
\i (00:01:53) fillin no
\t (00:01:53) Journal end - Fri Sep 16 12:49:55 2016
Version 15.0
START_MODULEORDER
@uob_hep_pc049a_lib.pc049a_toplevel(sch_1) 0 1 1 11 0
@uob_hep_pc049a_lib.pc049a_toplevel(sch_1):page1_i3@uob_hep_pc049a_lib.pc043c_single_maroc(sch_1) 0 1 12 3 0
@uob_hep_pc049a_lib.pc049a_toplevel(sch_1):page1_i3@uob_hep_pc049a_lib.pc043c_single_maroc(sch_1) 0 0 12 3 0
END_MODULEORDER
modules = { "local" : ["./ethernet/cfg" , "ipbus_core/cfg", "slaves/cfg" ] }
modules = { "local" : ["./ethernet/cfg" , "./ipbus_core/cfg", "./slaves/cfg" , "./sim/cfg" ] }
......@@ -6,10 +6,11 @@ files = [
"../../ethernet/coregen/gig_eth_pcs_pma_v11_4.xco",
"../hdl/eth_s6_1000basex.vhd",
"../hdl/emac_hostbus_decl.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd" ,
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd"
"../../../../ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd" ,
"../../../../ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd",
"../../../../ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd",
"../../../../ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd",
"../sim/eth_mac_sim.vhd"
]
......
......@@ -11,7 +11,7 @@
<msg type="warning" file="sim" num="100" delta="old" >The Simulation File Type &lt;<arg fmt="%s" index="1">Behavioral</arg>&gt; is not valid for this core. Overriding with File Type &lt;<arg fmt="%s" index="2">Structural</arg>&gt;.
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">VHDL simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;gig_eth_pcs_pma_v11_4&apos; already exists in the project. Output products for this core may be overwritten.</arg>
......@@ -26,10 +26,10 @@
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">BlackBox generator run option &apos;-p&apos; found multiple times. Only the first occurence is considered.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">VHDL simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pcs-pma.pdf with file from view xilinx_documentation</arg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pcs-pma.pdf with file from view xilinx_documentation</arg>
</msg>
<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
......
......@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.v&quot; into library work</arg>
</msg>
</messages>
......
......@@ -4,8 +4,8 @@ WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for this
Applying current project options...
Finished applying current project options.
Resolving generics for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
Overriding with simulation file type 'Structural'.
WARNING:sim - Verilog simulation file type 'Behavioral' is not valid for this
core. Overriding with simulation file type 'Structural'.
WARNING:sim - A core named 'gig_eth_pcs_pma_v11_4' already exists in the
project. Output products for this core may be overwritten.
Applying external generics to 'gig_eth_pcs_pma_v11_4'...
......@@ -19,17 +19,17 @@ WARNING:sim - BlackBox generator run option '-p' found multiple times. Only the
first occurence is considered.
Running synthesis for 'gig_eth_pcs_pma_v11_4'
Running ngcbuild...
Writing VHO instantiation template for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
Overriding with simulation file type 'Structural'.
Writing VHDL structural simulation model for 'gig_eth_pcs_pma_v11_4'...
Writing VEO instantiation template for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - Verilog simulation file type 'Behavioral' is not valid for this
core. Overriding with simulation file type 'Structural'.
Writing Verilog structural simulation model for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - Overwriting existing file
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus
/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pc
s-pma.pdf with file from view xilinx_documentation
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmwa
re/IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gi
g-eth-pcs-pma.pdf with file from view xilinx_documentation
Delivered 2 files into directory
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/
IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'gig_eth_pcs_pma_v11_4'...
......@@ -38,38 +38,38 @@ Generating ISE project...
XCO file found: gig_eth_pcs_pma_v11_4.xco
XMDF file found: gig_eth_pcs_pma_v11_4_xmdf.tcl
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.asy -view all -origin_type
imported
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/
IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.asy -view all
-origin_type imported
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc -view all -origin_type
created
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/
IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc -view all
-origin_type created
Checking file