Commit 3be81583 authored by David Cussans's avatar David Cussans

* Copied single_maroc schematic and layout from pc043

* Started to construct top level schematic

* Added some block diagrams




git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@13 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent e5bd77c1
DEFINE uob_hep_pc049a_lib worklib
INCLUDE $BRIS_CDSLIB/cds.lib
#INCLUDE $CERN_CDSLIB/lib_psd16.x/cds.lib
INCLUDE $CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/cds.lib
INCLUDE $CONCEPT_INST_DIR/share/cdssetup/cds.lib
{ Machine generated file created by SPI }
{ Last modified was 16:16:53 Thursday, March 13, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/pc043c_single_maroc/physical'
design_name 'pc043c_single_maroc'
design_library 'uob_hep_pc049a_lib'
library 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_discrete' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnconnector' 'cndiscrete' 'cnpassive' 'cnpld' 'cnpower' 'cnspecial' 'cnstandard' 'cnvlsi' 'standard' 'cnlinear'
temp_dir 'temp'
cpm_version '16.5'
session_name 'ProjectMgr58303345'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
EXCLUDE_PPT
INCLUDE_PPT
cdsprop_file ''
log_file ''
physical_path './worklib/pc043c_single_maroc/physical'
expand_with_errors 'OFF'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_SIZE '0.050'
DOC_GRID_SIZE '0.050'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PLOT_FONT 'Arial'
HPF_PLOTTER 'postscriptbw'
HPF_FONT 'native'
HPF_SPEC_PLOT_PAGESIZE 'YES'
HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc043c_single_maroc1.ps'
PLOTTER_FACILITY 'HPF'
PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '1'
PAPER_SOURCE '15'
WPLOTTER_NAME ''
HPF_PLOT_PAGESIZE 'A4'
HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4'
HPF_SCALEFACTOR '0.000000'
END_CONCEPTHDL
START_PKGRXL
comp_def_prop 'ALT_SYMBOLS' 'JEDEC_TYPE' 'MERGE_NC_PINS' 'MERGE_POWER_PINS' 'NC_PINS' 'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
comp_inst_prop 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'REUSE_ID' 'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL' 'VOLT_TEMP_SIGNAL_MODEL'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
USE_SUBDESIGN
FORCE_SUBDESIGN
GEN_SUBDESIGN
FILTER_PROPERTY
PASS_PROPERTY
FILTER_CONFLICTING_PROP
END_PKGRXL
START_DESIGNSYNC
replace_symbol '1'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'pc043c_single_maroc_27.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file '/projects/HEP_Instrumentation/cad/designs/uob_hep_pc049a/trunk/design_files/worklib/pc043c_single_maroc/bom/pc043c_single_maroc.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_VXL
run_directory './worklib/pc043c_single_maroc/cfg_verilog/sim1'
END_VXL
START_ECSET_MODELS
retain_existing_xnets_and_diffpairs 'NO'
END_ECSET_MODELS
START_VARIANT
last_variant_file 'variant.dat'
last_edit_type '2'
last_sorted_column 'REFDES'
pref_status_name 'Pref'
sort_style '0'
annotation_property_name 'VARIANT'
annotation_property_value '*'
annotation_DNIproperty_value 'DNI'
columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER'
END_VARIANT
START_ALLEGRO
hdl_padpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/pads' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/pads' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack_smd' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstacks/padstack3'
hdl_psmpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/symbols' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/symbols' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/connector' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/discrete'
hdl_topology_template_path '.' 'templates' '..' '../templates' '$CADENCE_INST_DIR/share/pcb/pcb_lib/templates' '$CADENCE_INST_DIR/share/pcb/allegrolib/templates'
END_ALLEGRO
{ Machine generated file created by SPI }
{ Last modified was 13:55:27 Thursday, March 13, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/pc049a_toplevel/physical'
design_name 'pc049a_toplevel'
design_library 'uob_hep_pc049a_lib'
library 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_discrete' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnconnector' 'cndiscrete' 'cnpassive' 'cnpld' 'cnpower' 'cnspecial' 'cnstandard' 'cnvlsi' 'standard' 'cnlinear'
temp_dir 'temp'
cpm_version '16.5'
session_name 'ProjectMgr58303345'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
EXCLUDE_PPT
INCLUDE_PPT
cdsprop_file ''
log_file ''
physical_path './worklib/pc049a_toplevel/physical'
expand_with_errors 'OFF'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_SIZE '0.050'
DOC_GRID_SIZE '0.050'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PLOT_FONT 'Arial'
HPF_PLOTTER 'postscriptbw'
HPF_FONT 'native'
HPF_SPEC_PLOT_PAGESIZE 'YES'
HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc049a_toplevel1.ps'
PLOTTER_FACILITY 'HPF'
PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '1'
PAPER_SOURCE '15'
WPLOTTER_NAME ''
HPF_PLOT_PAGESIZE 'A4'
HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4'
HPF_SCALEFACTOR '0.000000'
END_CONCEPTHDL
START_PKGRXL
comp_def_prop 'ALT_SYMBOLS' 'JEDEC_TYPE' 'MERGE_NC_PINS' 'MERGE_POWER_PINS' 'NC_PINS' 'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
comp_inst_prop 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'REUSE_ID' 'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL' 'VOLT_TEMP_SIGNAL_MODEL'
regenerate_physical_net_name 'OFF'
electrical_constraints 'OFF'
overwrite_constraints 'OFF'
USE_SUBDESIGN
FORCE_SUBDESIGN
GEN_SUBDESIGN
FILTER_PROPERTY
PASS_PROPERTY
FILTER_CONFLICTING_PROP
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'pc049a_toplevel_01.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file '/projects/HEP_Instrumentation/cad/designs/uob_hep_pc049a/trunk/design_files/worklib/pc049a_toplevel/bom/pc049a_toplevel.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_VXL
run_directory './worklib/pc049a_toplevel/cfg_verilog/sim1'
END_VXL
START_ECSET_MODELS
retain_existing_xnets_and_diffpairs 'NO'
END_ECSET_MODELS
START_ALLEGRO
hdl_padpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '$RAL_CDSLIB_PSD15/pads' '$BRIS_CDSLIB/pads' '$CERN_CDS_PADS/padstack_smd' '$CERN_CDS_PADS/padstacks/padstack3'
hdl_psmpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '$RAL_CDSLIB_PSD15/symbols' '$BRIS_CDSLIB/symbols' '$CERN_CDS_SYMBOLS/connector' '$CERN_CDS_SYMBOLS/discrete'
hdl_topology_template_path '.' 'templates' '..' '../templates' '$CADENCE_INST_DIR/share/pcb/pcb_lib/templates' '$CADENCE_INST_DIR/share/pcb/allegrolib/templates'
END_ALLEGRO
START_VARIANT
last_variant_file 'variant.dat'
last_edit_type '2'
last_sorted_column 'REFDES'
pref_status_name 'Pref'
sort_style '0'
annotation_property_name 'VARIANT'
annotation_property_value '*'
annotation_DNIproperty_value 'DNI'
columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER'
END_VARIANT
config pc043c_single_maroc;
design uob_hep_pc049a_lib.pc043c_single_maroc:sch_1;
liblist uob_hep_pc049a_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_discrete, bris_cds_logic, bris_cds_memory, bris_cds_pld, bris_cds_special, bris_cds_standard, bris_cds_switches, cn74lv, cn74tiac, cn75als, cncmos, cnconnector, cndiscrete, cnpassive, cnpld, cnpower, cnspecial, cnstandard, cnvlsi, standard, cnlinear;
viewlist chips, pic_1, picopt_1, sch_1, schematic, entity, functional;
stoplist chips;
endconfig
config pc043c_single_maroc;
design uob_hep_pc043a_lib.pc043c_single_maroc:sch_1;
liblist uob_hep_pc043a_lib, bris_cds_standard, standard, cnconnector, cndiscrete, cnlinear, cnstandard, cnpassive, cnpower, cnspecial, bris_cds_connectors, bris_cds_analogue;
viewlist edif, vlog_rtl, vhdl_rtl, sch_1, entity;
stoplist none;
endconfig
config pc043c_single_maroc;
design uob_hep_pc043a_lib.pc043c_single_maroc:sim_sch_1;
liblist uob_hep_pc043a_lib, bris_cds_standard, standard, cnconnector, cndiscrete, cnlinear, cnstandard, cnpassive, cnpower, cnspecial, bris_cds_connectors, bris_cds_analogue;
viewlist vlog_map, hw_map, swift_map, vlog_model, hw_model, swift_model, vlog_structural, vlog_rtl, vlog_behavioral, vlog_system, mcvlog, pic_1, picopt_1, tbl_1, sim_sch_1, sch_1, entity;
stoplist vlog_model, swift_model;
endconfig
config pc043c_single_maroc;
design uob_hep_pc043a_lib.pc043c_single_maroc:sim_sch_1;
liblist uob_hep_pc043a_lib, bris_cds_standard, standard, cnconnector, cndiscrete, cnlinear, cnstandard, cnpassive, cnpower, cnspecial, bris_cds_connectors, bris_cds_analogue;
viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl_system, mc_arch, pic_1, picopt_1, sim_sch_1, sch_1;
stoplist none;
endconfig
// generated by newgenasym Thu Mar 13 15:25:04 2014
module pc043c_single_maroc (adc_dav, analog_in, ck_40m, ck_r, ck_sc, ckb_40m, ctest,
d_r, d_sc, en_otag, hold1, hold2, \or , out_adc, qbuf_r,
qbuf_sc, rstb_r, rstn_adc, rstn_sc, start_adcb, sum, trig);
output adc_dav;
input [63:0] analog_in;
input ck_40m;
input ck_r;
input ck_sc;
input ckb_40m;
input ctest;
input d_r;
input d_sc;
input en_otag;
input hold1;
input hold2;
output [1:0] \or ;
output out_adc;
output qbuf_r;
output qbuf_sc;
input rstb_r;
input rstn_adc;
input rstn_sc;
input start_adcb;
output [8:1] sum;
output [63:0] trig;
initial
begin
end
endmodule
-- generated by newgenasym Thu Mar 13 15:25:04 2014
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity pc043c_single_maroc is
port (
ADC_DAV: OUT std_logic;
ANALOG_IN: IN std_logic_vector (63 DOWNTO 0);
CK_40M: IN std_logic;
CK_R: IN std_logic;
CK_SC: IN std_logic;
CKB_40M: IN std_logic;
CTEST: IN std_logic;
D_R: IN std_logic;
D_SC: IN std_logic;
EN_OTAG: IN std_logic;
HOLD1: IN std_logic;
HOLD2: IN std_logic;
\or\: OUT std_logic_vector (1 DOWNTO 0);
OUT_ADC: OUT std_logic;
QBUF_R: OUT std_logic;
QBUF_SC: OUT std_logic;
RSTB_R: IN std_logic;
RSTN_ADC: IN std_logic;
RSTN_SC: IN std_logic;
START_ADCB: IN std_logic;
SUM: OUT std_logic_vector (8 DOWNTO 1);
TRIG: OUT std_logic_vector (63 DOWNTO 0));
end pc043c_single_maroc;
(Pinlist
(Pin
(Name TRIG)
(MSB 63)
(LSB 0)
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name SUM)
(MSB 8)
(LSB 1)
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name QBUF_SC)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name QBUF_R)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name OUT_ADC)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name OR)
(MSB 1)
(LSB 0)
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name BUF_OUT_Q)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name BUF_OUT_FS)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name ADC_DAV)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name VL)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name VH)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name START_ADCB)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name RSTN_SC)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name RSTN_ADC)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape Line)
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name RSTB_R)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )