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Scalable MAROC Charge Sensitive Readout
Commit 3c6b2988 authored by David Cussans's avatar David Cussans
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Checking in files after doing most of Erik S's changes 

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@17 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent f862dbf7
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Showing with 1063464 additions and 27966 deletions
design_files/pc049a_toplevel.cpm
View file @ 3c6b2988
{ Machine generated file created by SPI } { Machine generated file created by SPI }
{ Last modified was 16:44:58 Thursday, June 12, 2014 } { Last modified was 20:49:15 Monday, July 28, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by } { NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. } { SPI, your modifications will be overwritten. }
...@@ -68,7 +68,7 @@ create_user_prop 'NO' ...@@ -68,7 +68,7 @@ create_user_prop 'NO'
run_packager 'YES' run_packager 'YES'
run_netrev 'YES' run_netrev 'YES'
backannotate_forward 'NO' backannotate_forward 'NO'
last_board_file 'pc049a_toplevel_23.brd' last_board_file 'pc049a_toplevel_29.brd'
run_feedback 'YES' run_feedback 'YES'
run_genfeedformat 'YES' run_genfeedformat 'YES'
backannotate_feedback 'NO' backannotate_feedback 'NO'
......
design_files/worklib/pc043c_single_maroc/sch_1/page3.cpc
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...@@ -431,10 +431,10 @@ ...@@ -431,10 +431,10 @@
cnpower avdd * cnpower avdd *
page3_i250 page3_i250
#CELL #CELL
cnpassive elcaptan * cnpassive capcersmdcl2 *
page3_i252 page3_i252
#CELL #CELL
cnlinear tps776xx * bris_cds_analogue lm2937imp *
page3_i253 page3_i253
#ISCELL #ISCELL
standard inport * standard inport *
......
design_files/worklib/pc043c_single_maroc/sch_1/pc.db
View file @ 3c6b2988
-- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 16.5-S029 (v16-5-13BU) 8/27/2012 on Wed Mar 19 17:51:42 2014 -- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 16.6-S014 (v16-6-112AQ) 7/29/2013 on Mon Jul 28 09:39:05 2014
#ISCELL #ISCELL
bris_cds_standard a3-2000 * bris_cds_standard a3-2000 *
* *
...@@ -1137,10 +1137,10 @@ ...@@ -1137,10 +1137,10 @@
cnpower avdd * cnpower avdd *
page3_i250 page3_i250
#CELL #CELL
cnpassive elcaptan * cnpassive capcersmdcl2 *
page3_i252 page3_i252
#CELL #CELL
cnlinear tps776xx * bris_cds_analogue lm2937imp *
page3_i253 page3_i253
#ISCELL #ISCELL
standard inport * standard inport *
......
design_files/worklib/pc043c_single_maroc/sch_1/pc043c_single_maroc.con
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( (
(version 16.5) (version 16.6)
(tool (tool
(creator "csnetlister") (creator "csnetlister")
(last "csnetlister") (last "csnetlister")
...@@ -7,9 +7,9 @@ ...@@ -7,9 +7,9 @@
(library "uob_hep_pc049a_lib") (library "uob_hep_pc049a_lib")
(design "pc043c_single_maroc" (design "pc043c_single_maroc"
(lastIds (lastIds
(lastInstanceId 278) (lastInstanceId 282)
(lastNetId 113) (lastNetId 113)
(lastInstTermId 680) (lastInstTermId 690)
) )
(cells (cells
("S2" "maroc3" "bris_cds_analogue" "sym_1" ("S2" "maroc3" "bris_cds_analogue" "sym_1"
...@@ -318,24 +318,6 @@ ...@@ -318,24 +318,6 @@
("T348" "k<SIZE-1..0>" -1 -1 3) ("T348" "k<SIZE-1..0>" -1 -1 3)
) )
) )
("S18" "elcaptan" "cnpassive" "sym_1"
(params
("size" "1")
)
(terms
("T373" "a<SIZE-1..0>" -1 -1 3)
("T374" "b<SIZE-1..0>" -1 -1 3)
)
)
("S19" "tps776xx" "cnlinear" "sym_1"
(terms
("T375" "en*" -1 -1 1)
("T376" "gnd" -1 -1 1)
("T377" "in" 2 1 1)
("T378" "out" 2 1 2)
("T379" "pg" -1 -1 1)
)
)
("S20" "rsmd0402" "cnpassive" "sym_2" ("S20" "rsmd0402" "cnpassive" "sym_2"
(params (params
("size" "1") ("size" "1")
...@@ -345,6 +327,14 @@ ...@@ -345,6 +327,14 @@
("T381" "b<SIZE-1..0>" -1 -1 3) ("T381" "b<SIZE-1..0>" -1 -1 3)
) )
) )
("S21" "lm2937imp" "bris_cds_analogue" "sym_1"
(terms
("T406" "gnd" -1 -1 1)
("T407" "gnd_tab" -1 -1 1)
("T408" "pinput" -1 -1 3)
("T409" "poutput" -1 -1 3)
)
)
) )
(nets (nets
...@@ -1592,20 +1582,6 @@ ...@@ -1592,20 +1582,6 @@
) )
) )
) )
("I24" "page2_i30" "S3"
(pins
("M218" "T143" 0 0
(conn
("0" 0 0 "N18" -1 -1)
)
)
("M219" "T144" 0 0
(conn
("0" 0 0 "N7" -1 -1)
)
)
)
)
("I25" "page2_i31" "S4" ("I25" "page2_i31" "S4"
(pins (pins
("M220" "T145" 0 0 ("M220" "T145" 0 0
...@@ -1948,20 +1924,6 @@ ...@@ -1948,20 +1924,6 @@
) )
) )
) )
("I53" "page2_i79" "S3"
(pins
("M266" "T143" 0 0
(conn
("0" 0 0 "N19" -1 -1)
)
)
("M267" "T144" 0 0
(conn
("0" 0 0 "N7" -1 -1)
)
)
)
)
("I54" "page2_i81" "S6" ("I54" "page2_i81" "S6"
(pins (pins
("M268" "T192" 0 0 ("M268" "T192" 0 0
...@@ -3577,72 +3539,96 @@ ...@@ -3577,72 +3539,96 @@
) )
) )
) )
("I275" "page3_i252" "S18" ("I277" "page1_i146" "S20"
(pins (pins
("M670" "T373" 0 0 ("M677" "T380" 0 0
(conn (conn
("0" 0 0 "N80" -1 -1) ("0" 0 0 "N5" -1 -1)
)
)
("M678" "T381" 0 0
(conn
("0" 0 0 "N2" 0 0)
)
)
)
)
("I278" "page1_i147" "S20"
(pins
("M679" "T380" 0 0
(conn
("0" 0 0 "N6" -1 -1)
)
)
("M680" "T381" 0 0
(conn
("0" 0 0 "N2" 1 1)
) )
) )
("M671" "T374" 0 0 )
)
("I279" "page3_i252" "S6"
(pins
("M681" "T192" 0 0
(conn (conn
("0" 0 0 "N9" -1 -1) ("0" 0 0 "N9" -1 -1)
) )
) )
("M682" "T193" 0 0
(conn
("0" 0 0 "N80" -1 -1)
)
)
) )
) )
("I276" "page3_i253" "S19" ("I280" "page3_i253" "S21"
(pins (pins
("M672" "T375" -1 -1 ("M683" "T406" -1 -1
(conn (conn
("0" -1 -1 "N9" -1 -1) ("0" -1 -1 "N9" -1 -1)
) )
) )
("M673" "T376" -1 -1 ("M684" "T407" -1 -1
(conn (conn
("0" -1 -1 "N9" -1 -1) ("0" -1 -1 "N9" -1 -1)
) )
) )
("M674" "T377" 2 1 ("M685" "T408" -1 -1
(conn (conn
("0" 2 2 "N7" -1 -1) ("0" -1 -1 "N7" -1 -1)
("0" 1 1 "N7" -1 -1)
) )
) )
("M675" "T378" 2 1 ("M686" "T409" -1 -1
(conn (conn
("0" 2 2 "N80" -1 -1) ("0" -1 -1 "N80" -1 -1)
("0" 1 1 "N80" -1 -1)
) )
) )
("M676" "T379" -1 -1
)
) )
) )
("I277" "page1_i146" "S20" ("I281" "page2_i30" "S20"
(pins (pins
("M677" "T380" 0 0 ("M687" "T380" 0 0
(conn (conn
("0" 0 0 "N5" -1 -1) ("0" 0 0 "N18" -1 -1)
) )
) )
("M678" "T381" 0 0 ("M688" "T381" 0 0
(conn (conn
("0" 0 0 "N2" 0 0) ("0" 0 0 "N7" -1 -1)
) )
) )
) )
) )
("I278" "page1_i147" "S20" ("I282" "page2_i79" "S20"
(pins (pins
("M679" "T380" 0 0 ("M689" "T380" 0 0
(conn (conn
("0" 0 0 "N6" -1 -1) ("0" 0 0 "N19" -1 -1)
) )
) )
("M680" "T381" 0 0 ("M690" "T381" 0 0
(conn (conn
("0" 0 0 "N2" 1 1) ("0" 0 0 "N7" -1 -1)
) )
) )
) )
......
design_files/worklib/pc049a_fpga/chips/chips.prt
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...@@ -150,7 +150,7 @@ primitive 'PC049A_FPGA'; ...@@ -150,7 +150,7 @@ primitive 'PC049A_FPGA';
INPUT_LOAD='(-0.01,0.01)'; INPUT_LOAD='(-0.01,0.01)';
OUTPUT_LOAD='(1.0,-1.0)'; OUTPUT_LOAD='(1.0,-1.0)';
'SATA_RXN_I'<0>: 'SATA_RXN_I'<0>:
PIN_NUMBER='(0,D13,0,0,0,0,0,0)'; PIN_NUMBER='(0,C13,0,0,0,0,0,0)';
CONSTRAINT='LOCATED'; CONSTRAINT='LOCATED';
IO_REGISTER='NO'; IO_REGISTER='NO';
SIGNAL_INTEGRITY='NONE'; SIGNAL_INTEGRITY='NONE';
...@@ -164,7 +164,7 @@ primitive 'PC049A_FPGA'; ...@@ -164,7 +164,7 @@ primitive 'PC049A_FPGA';
IOB_DELAY='NONE'; IOB_DELAY='NONE';
INPUT_LOAD='(-0.01,0.01)'; INPUT_LOAD='(-0.01,0.01)';
'SATA_RXP_I'<0>: 'SATA_RXP_I'<0>:
PIN_NUMBER='(0,C13,0,0,0,0,0,0)'; PIN_NUMBER='(0,D13,0,0,0,0,0,0)';
CONSTRAINT='LOCATED'; CONSTRAINT='LOCATED';
IO_REGISTER='NO'; IO_REGISTER='NO';
SIGNAL_INTEGRITY='NONE'; SIGNAL_INTEGRITY='NONE';
...@@ -178,7 +178,7 @@ primitive 'PC049A_FPGA'; ...@@ -178,7 +178,7 @@ primitive 'PC049A_FPGA';
IOB_DELAY='NONE'; IOB_DELAY='NONE';
INPUT_LOAD='(-0.01,0.01)'; INPUT_LOAD='(-0.01,0.01)';
'SATA_TXN_O'<0>: 'SATA_TXN_O'<0>:
PIN_NUMBER='(0,B14,0,0,0,0,0,0)'; PIN_NUMBER='(0,A14,0,0,0,0,0,0)';
CONSTRAINT='LOCATED'; CONSTRAINT='LOCATED';
IO_REGISTER='NO'; IO_REGISTER='NO';
SIGNAL_INTEGRITY='NONE'; SIGNAL_INTEGRITY='NONE';
...@@ -190,7 +190,7 @@ primitive 'PC049A_FPGA'; ...@@ -190,7 +190,7 @@ primitive 'PC049A_FPGA';
SIGNAL_INTEGRITY='NONE'; SIGNAL_INTEGRITY='NONE';
OUTPUT_LOAD='(1.0,-1.0)'; OUTPUT_LOAD='(1.0,-1.0)';
'SATA_TXP_O'<0>: 'SATA_TXP_O'<0>:
PIN_NUMBER='(0,A14,0,0,0,0,0,0)'; PIN_NUMBER='(0,B14,0,0,0,0,0,0)';
CONSTRAINT='LOCATED'; CONSTRAINT='LOCATED';
IO_REGISTER='NO'; IO_REGISTER='NO';
SIGNAL_INTEGRITY='NONE'; SIGNAL_INTEGRITY='NONE';
......
design_files/worklib/pc049a_fpga/entity/pc.db
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-- pcdb file, Rev:1.0 written by VAN 31.09-p01 on Jun 2, 2014 09:45:05 -- pcdb file, Rev:1.0 written by VAN 31.09-p01 on Jul 28, 2014 18:45:07
design_files/worklib/pc049a_fpga/entity/verilog.v
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// generated by newgenasym Mon Jun 2 09:45:05 2014 // generated by newgenasym Mon Jul 28 18:45:07 2014
module pc049a_fpga (adc_dav_i, button1_i, button2_i, cclk, ck_40m_n_o, module pc049a_fpga (adc_dav_i, button1_i, button2_i, cclk, ck_40m_n_o,
......
design_files/worklib/pc049a_fpga/entity/vhdl.vhd
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-- generated by newgenasym Mon Jun 2 09:45:05 2014 -- generated by newgenasym Mon Jul 28 18:45:07 2014
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
......
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config pc049a_toplevel;
design uob_hep_pc049a_lib.pc049a_toplevel:sch_1;
liblist uob_hep_pc049a_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_discrete, bris_cds_logic, bris_cds_memory, bris_cds_pld, bris_cds_special, bris_cds_standard, bris_cds_switches, cn74lv, cn74tiac, cn75als, cncmos, cnconnector, cndiscrete, cnpassive, cnpld, cnpower, cnspecial, cnstandard, cnvlsi, standard, cnlinear, cnmemory, cninterface, cnmech, cnmicro, help, cn100e, cn10e, cn10el, cn10k, cn10kh;
viewlist edif, vlog_rtl, vhdl_rtl, sch_1, entity;
stoplist none;
endconfig
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expand.cfg
\ No newline at end of file
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config pc049a_toplevel;
design uob_hep_pc049a_lib.pc049a_toplevel:sim_sch_1;
liblist uob_hep_pc049a_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_discrete, bris_cds_logic, bris_cds_memory, bris_cds_pld, bris_cds_special, bris_cds_standard, bris_cds_switches, cn74lv, cn74tiac, cn75als, cncmos, cnconnector, cndiscrete, cnpassive, cnpld, cnpower, cnspecial, cnstandard, cnvlsi, standard, cnlinear, cnmemory, cninterface, cnmech, cnmicro, help, cn100e, cn10e, cn10el, cn10k, cn10kh;
viewlist vlog_map, hw_map, swift_map, vlog_model, hw_model, swift_model, vlog_structural, vlog_rtl, vlog_behavioral, vlog_system, mcvlog, pic_1, picopt_1, tbl_1, sim_sch_1, sch_1, entity;
stoplist vlog_model, swift_model;
endconfig
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sed -re 's/09 73 296 6801/09-73-296-6801/;s/09 03 196 6921/09-03-196-6921/' dialcnet.dat > dialcnet_edited.dat
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