Starting to write simulation test-bench

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@31 e1591323-3689-4d5a-aa31-d1a7cbdc5706

Starting to write simulation test-bench
git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@31 e1591323-3689-4d5a-aa31-d1a7cbdc5706
42660563 · David Cussans · de1cbaf1 · 42660563 · 42660563 · 42660563
Commit 42660563 authored Mar 31, 2015 by David Cussans
4 changed files
--- a/firmware/hdl/IPBusInterfaceGTP_rtl.vhd
+++ b/firmware/hdl/IPBusInterfaceGTP_rtl.vhd
@@ -46,7 +46,8 @@ use work.emac_hostbus_decl.all;

 ENTITY IPBusInterfaceGTP IS
   GENERIC( 
-      NUM_EXT_SLAVES : positive := 5
+      NUM_EXT_SLAVES : positive := 5; --! Number of IPBus slaves outside IPBusInterfaceGTP module 
+      BUILD_SIMULATED_ETHERNET : integer := 0 --! Set to 1 to build simulated Ethernet interface using Modelsim FLI
   );
   PORT(

@@ -137,6 +138,9 @@ BEGIN
 --      In this version, consists of hard MAC core + GTP transceiver
 --      Can be replaced by any other MAC / PHY combination

+  --! By default generate a Gigabit serial MAC
+    generate_physicalmac: if ( BUILD_SIMULATED_ETHERNET /= 1 ) generate
+
      eth: entity work.eth_s6_1000basex port map(
          gtp_clkp => gtp_clkp,
          gtp_clkn => gtp_clkn,
@@ -161,13 +165,30 @@ BEGIN
          rx_last => mac_rx_last,
          rx_error => mac_rx_error
          );
+    end generate generate_physicalmac;
+
+  --! Set generic BUILD_SIMULATED_ETHERNET to 1 to generate a simulated MAC
+    generate_simulatedmac: if ( BUILD_SIMULATED_ETHERNET = 1 ) generate
+      simulated_eth: entity work.eth_mac_sim
+        port map(
+          clk => clk125,
+          rst => rst,
+          tx_data => mac_tx_data,
+          tx_valid => mac_tx_valid,
+          tx_last => mac_tx_last,
+          tx_error => mac_tx_error,
+          tx_ready => mac_tx_ready,
+          rx_data => mac_rx_data,
+          rx_valid => mac_rx_valid,
+          rx_last => mac_rx_last,
+          rx_error => mac_rx_error
+          );
+    end generate generate_simulatedmac;
  
 	phy_rstb_o <= '1';
 	
 -- ipbus control logic
        ipbus: entity work.ipbus_ctrl
-          generic map (
-            BUFWIDTH => 2)
          port map(
            mac_clk => clk125,
            rst_macclk => rst_125,

--- a/firmware/hdl/ipbus_addr_decode.vhd
+++ b/firmware/hdl/ipbus_addr_decode.vhd
--- a/firmware/sim/hdl/pc049a_demo_tb.vhd
+++ b/firmware/sim/hdl/pc049a_demo_tb.vhd
--- a/firmware/top/pc049a/demo/pc049a_top.vhd
+++ b/firmware/top/pc049a/demo/pc049a_top.vhd
@@ -67,7 +67,8 @@ use work.wishbone_pkg.all;
 entity pc049a_top is
  generic
    (
-      BUILD_WHITERABBIT : integer := 0     -- set to 1 to synthesize White Rabbit cores
+      BUILD_WHITERABBIT : integer := 0;       --! set to 1 to synthesize White Rabbit cores
+      BUILD_SIMULATED_ETHERNET : integer := 0 --! set to 1 to build with simulated Ethernet interface using Modelsim FLI
      );
  port
    (
@@ -851,8 +852,7 @@ begin

  IPBusInterface_inst : entity work.IPBusInterfaceGTP
    GENERIC MAP (
-      NUM_EXT_SLAVES => c_NMAROC_SLAVES+1 --! Total number of IPBus slave
-                                          --busses = number in MAROC +1
+      NUM_EXT_SLAVES => c_NMAROC_SLAVES+1 --! Total number of IPBus slave busses = number in MAROC plus one for External IO
      )
    PORT MAP (